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I am working on a class AB amplifier circuit to that can output both AC and DC current, controlled by an op-amp with feedback from the final output. The output will be driving an 50uH inductor. enter image description here

The inductor introduced instability into the system, which I am trying to over come with C1 and R4. I then used the technique introduced by this video by LT to get the simulated phase margin:

  1. Modified circuit to use the technique in the video: enter image description here
  2. Result: enter image description here

The phase-shift at ~0 dB is ~ 99 degrees. This equals to phase margin of 99 degrees (right?)

To confirm the result is correct, I simulated the same circuit with a different technique, by applying a step signal (10 mV) at the input, and measure the overshoot%, which was introduced in this video by TI.

The circuit: enter image description here

The result: enter image description here

As can be seen, there is massive overshoot which does not confirm the result from technique 1. Why is this? Did I do something wrong?

Edit: Estimation of the inductor value was 5uH, real value measured is 50uH

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  • \$\begingroup\$ One general comment: A fixed relation between the phase margin found by loop gain analysis resp. overshoot (time domain) does exist for a 2nd-order LINEAR a´circuit only. \$\endgroup\$
    – LvW
    Commented Jun 25 at 18:31
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    \$\begingroup\$ Zhi, you don't show the time axis on the bottom graph. What exactly is the ringing frequency? Expand that diagram and show us both time and peak-to-peak timing (so we can get f out of it.) You have an insanely quick shift in phase on your diagram. Your system has very high gain. This doesn't bode well (pun intended.) \$\endgroup\$ Commented Jun 25 at 20:15
  • \$\begingroup\$ Your text says the inductor is 5mH, but the images shows it to be 5uH, ie: 1000 times smaller. Which is correct? \$\endgroup\$ Commented Jun 26 at 3:47
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    \$\begingroup\$ The technique is the classical middlebrook technique from the 70s (though they don't say so in the LTspice video) and it's correct. You forgot about the gain margin, which is non-existent in your design; you got positive LG when the phase does 180deg turn, so I'm not surprised you still see ringing. \$\endgroup\$
    – Designalog
    Commented Jun 26 at 8:17
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    \$\begingroup\$ @Zhi - no, in contrary. The phase margin concept was found and defined for the loop gain response only. Therefore, the phase margin determination on the basis of loop gain is applicable not only for 2nd-order systems. \$\endgroup\$
    – LvW
    Commented Jul 2 at 13:08

2 Answers 2

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The phase-shift at ~0 dB is ~ 99 degrees. This equals to phase margin of 99 degrees (right?)

You may be interpreting the results of the AC simulation incorrectly. It seems you have followed the instructions in the video correctly, but perhaps did not fully appreciate how to interpret the results.

As well as phase margin, you need to consider gain margin, which is defined as the loop gain at the frequency where the phase crosses the zero line in your diagram. To be stable, the gain must be less than 1 ie: below 0dB at this frequency. In general, a phase margin of 30–60 degrees and a gain margin of between -2 to -10 dB are desirable in the closed-loop system design.

The Bode plot you posted shows a zone where:

  1. Phase crosses zero in the region from ~30kHz to ~70kHz, and
  2. gain remains well above 0dB (~40dB).

Refer to the image below (which is your Bode plot with my mark-ups).

This tells us that it is very likely to oscillate or have a very under-damped response - which is what you found in the time-domain simulation.

enter image description here

Solution:

Try tuning your feedback controller. By adding more gain at low frequency, and rolling off the gain carefully at high frequency, a much better response is possible without having to put resistors to damp out the oscillations.

Notes:

  1. I didn't have the same transistor models as per the OP, so I used the same output transistors as @RussellH.
  2. I added a resistor to help bias the first transistors in the Darlington pairs.
  3. B1 and B2 compare the ideal output with the output for each amplifier, to give an error.

Image below: LTspice house- keeping.
enter image description here

Image below: The original circuit.
enter image description here

Image below: The new circuit. Note the changed feedback arrangements. All other aspects of the new circuit are identical to the original.

enter image description here

Image below: Time-domain response of each circuit to a positive pulse, and a negative pulse (100us between edges) with Riso (damping series resistor) set to a negligible value (0.1mΩ).

enter image description here

Image below: Bode plots for each circuit, showing clearly that the improved circuit (red trace) has much better phase and gain margin than the original circuit (green trace).

enter image description here

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    \$\begingroup\$ +1 Nice demonstration. \$\endgroup\$
    – RussellH
    Commented Jun 26 at 17:12
  • \$\begingroup\$ Thank you for the detailed answer @Fabio, but I do have the following questions: 1. Can the loop gain analysis method be used for this circuit? From LvW's comment on the original post, it seems to me that this method is not suitable for such circuit. \$\endgroup\$
    – Zhi
    Commented Jul 2 at 11:17
  • \$\begingroup\$ 2. Could you please explain more about the value choices for the resistor and the capacitor on the feedback path? I have recently measured the inductor's value, and it is actually 50uH(see edit on OG post). Moreover, this circuit would ideally be able to drive 4 of these inductors in parallel(this is a tester for fluxgate current sensors, AC and DC current is applied then the output of the sensors are measured. The wire through the magnetic core of the fluxgate current sensor would then become a 1-turn winding on the core) \$\endgroup\$
    – Zhi
    Commented Jul 2 at 11:23
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    \$\begingroup\$ @Zhi Answering your questions: Q3. The 1ohm is only there to allow me to measure op-amp current in the sim, not needed for real circuit. The 1k provided bias current for Q1 & Q2 to keep them in class A. \$\endgroup\$ Commented Jul 5 at 22:51
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    \$\begingroup\$ Q1. Yes, the loop method can be applied - you can see the result in my post, last chart. \$\endgroup\$ Commented Jul 5 at 22:52
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I spent some time with this and can now provide a better answer. I will leave the existing discussion for comparison.

In the video by LT, the first attempt to stabilize the capacitive load was a series resistor with the capacitor. Only then was the feedback compensation applied. I chose a series resistor also to damp the oscillations, but I knew at the time it was not power efficient.

A better choice for an inductor is a parallel resistor. This will allow the resistor to dominate high frequencies and the inductor dominate the low frequencies. So I start there without the U1 feedback capacitor and the 1k feedback resistor set to zero. R4 is stepped through 3 values in a transient analysis and using the method in the video in an ac sweep.

The results show that there is a sweet spot for R4 at approximately 1 ohm. The phase margin indicated for the blue plot is 77 degrees. The red phase margin is about 13 degrees. The green phase margin is about 30degrees.

Comparing the transient % overshoot with the phase-margin chart in this video from LT gives good agreement.

enter image description here

enter image description here

enter image description here

The results here are good enough that feedback compensation should not be required. Since this is a unity gain non-inverting amplifier, then Ri in (1+Rf/Ri) is infinite making any feedback dependent on the op-amp input characteristics.

The feedback capacitor C3 around U2 may be required for local compensation. The inductor will have a series resistance that will influence the operation. I found that a small value actually reduces the low frequency ringing. Resistance in the feedback path can slow down the response.

Anyway. You can start where I left off. Hope this helps.



The above discussion supersedes this one, left here for reference.

The inductor forms a resonant path through the collector-emitter capacitance of the power Tx, through the power supply (decoupling capacitor) to ground and back through R1. A second path through the base-emitter of the power TX and then through the collector-emitter capacitance of the driver to the same return path. Placing a resistor in series with the inductor will get rid of the ringing. This comes with a power dissipation cost. Anyway that is where the oscillation is coming from. Because R1 is so low, the path is underdamped.

The simulation uses different components than in the OP, but the ringing occurs just the same. The three plots are for different values of the resistor in series with the inductor.

enter image description here

Improvements from Fabio's comments. The frequency response of the output node is shown in the upper panel below. The loop-gain is shown in the lower panel as V(vf)/V(vn).

A clear improvement in phase margin of the loop-gain is shown under the peak as the damping resistor increases.

enter image description here

enter image description here

I don't have a good power efficient solution for you since I don't understand the loading requirements that the circuit is being used for. Regardless the resonant loop needs damping.

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  • \$\begingroup\$ I noticed the Bode plot is of one node, v(n001), rather than the ratio of two node voltages, which is different to what the OP presented, and what was presented in the LT spice video. Is there a reason for that? \$\endgroup\$ Commented Jun 27 at 2:35
  • \$\begingroup\$ Thanks @FabioBarone . You are right. The Bode plot is of the output/feedback signal. I will adjust my answer. \$\endgroup\$
    – RussellH
    Commented Jun 27 at 3:13
  • \$\begingroup\$ No worries, however, I might suggest applying some caution here, it may be prudent to plot all three traces separately: the numerator (FB), the denominator (opamp -ve input), and the ratio. I just had an interesting case where the plot of the ratio predicted very stable behaviour (very much single dominant pole), yet the step response was very under-damped. When I plotted the FB and op-amp nodes, both traces showed gain peaking & a very rapid phase shift all at the same frequency. Perhaps the math (division) got confused? \$\endgroup\$ Commented Jun 27 at 3:21
  • \$\begingroup\$ So perhaps this method has a caveat: check the numerator and denominator before jumping to conclusions about their ratio. Perhaps I should post this as a question; perhaps others have had similar experiences, and can perhaps advise how to go about (a) identifying when this can be an issue, and (b) how to apply the simulation tools better in those circumstances. \$\endgroup\$ Commented Jun 27 at 3:22
  • \$\begingroup\$ I have updated my answer. The focus of my answer is still the damping resistor solution. The added loop-gain response further clarifies my observation. My last sentence still applies. @FabioBarone \$\endgroup\$
    – RussellH
    Commented Jun 27 at 3:40

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