# parasitic fringe capcitance calculation

I'm calculating the parasitic fringe capacitance between METAL1 line and substrate in a VLSI circuit. I'm using the equation for a cylindric capacitor:

$C = \dfrac{2 \pi \cdot \epsilon \cdot l}{log (\frac{t}{h})}$ (where t is dielectric thickness, and h is the metal height)

My questions:

• When I calculate the parasitic capacitance between two metal lines in VLSI, can I use the equation for parallel plates:

$C = \dfrac{\epsilon \cdot h \cdot l}{d}$ (where d is the distance between the two metals)?

• How does the applied voltage to one line influence the second line?

– user17592
Commented Jun 6, 2013 at 9:29
• 2*piepsilon/log(t/h) for the fringe capacitance and epsilonh*l/t (t - distance between metals) for metal to metal capacitance.
– Vova
Commented Jun 6, 2013 at 10:13
• yes the log is natural Commented Jun 6, 2013 at 16:41

Here is the Capacitance Calculation for Cylindrical lines.As stated by you the formula $$C = \dfrac{\epsilon \cdot h \cdot l}{d}$$ is used only and strictly for sheet capacitors.Here the METAL layes act like line charges.