I'm calculating the parasitic fringe capacitance between METAL1 line and substrate in a VLSI circuit. I'm using the equation for a cylindric capacitor:

\$ C = \dfrac{2 \pi \cdot \epsilon \cdot l}{log (\frac{t}{h})} \$ (where t is dielectric thickness, and h is the metal height)

My questions:

  • Is the log in the equation natural, or base 10?

  • When I calculate the parasitic capacitance between two metal lines in VLSI, can I use the equation for parallel plates:

    \$ C = \dfrac{\epsilon \cdot h \cdot l}{d} \$ (where d is the distance between the two metals)?

  • How does the applied voltage to one line influence the second line?

  • 1
    \$\begingroup\$ What equations are you talking about? Please show them in your question. \$\endgroup\$
    – user17592
    Commented Jun 6, 2013 at 9:29
  • \$\begingroup\$ 2*piepsilon/log(t/h) for the fringe capacitance and epsilonh*l/t (t - distance between metals) for metal to metal capacitance. \$\endgroup\$
    – Vova
    Commented Jun 6, 2013 at 10:13
  • \$\begingroup\$ yes the log is natural \$\endgroup\$ Commented Jun 6, 2013 at 16:41

1 Answer 1


The operating angular frequency for VLSI chip is high compared to Physical dimensions of the METAL1 Layer, thus the metal layers are considered of infinite length for effective capacitance calculation.

Here is the Capacitance Calculation for Cylindrical lines.As stated by you the formula $$ C = \dfrac{\epsilon \cdot h \cdot l}{d} $$ is used only and strictly for sheet capacitors.Here the METAL layes act like line charges.

Secondly since the routing of metal lines is done in very compact way there is an effect called crosstalking


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