# 5V Tolerance of 3.3V OUTPUT pin

Let's assume the following scenario:

• uC (@3.3V VDD) drives an I/O pin HIGH 3.3V (just to be clear, it's not an open-drain pin, so the p-channel mosfet of the output pin is actually driving the pin to VDD level)
• Pin is also rated as a 5V tolerant input (so it's not clamped to VDD).
• The line that the pin is driving is also connected to a pin of another uC(@5V VDD) which may drive the line to 5V level also
• Between the two pins of the different uC's we assume an ~2470R resistance

The questions are:

What happens if while the 3.3V uC drives the line HIGH (3.3V), the other uC also tries to drive the line HIGH (5V)? What can then be stated about the 5V tolerance of the 3.3VDD uC OUTPUT pin?

Is then a 680uA current ( (5 - 3.3) / 2470 ) sinked to the VDD of the 1st uC? What does actually happen inside the I/O pin circuitry of the 1st uC? Is this inter-connection safe?

I post this question in case someone with a better understanding of is cares to answer, as this case is not documented in the uC datasheet and I couldn't find any definitive reference on this after doing a fair bit of research.

• Why are the two output pins being allowed to actively drive a signal in the first place? – Ignacio Vazquez-Abrams Jun 6 '13 at 14:21
• Well, this is on an I2C bus and a bi-directional level converter is not an option (due to other constraints) – Nitro Jun 6 '13 at 14:26
• I2C is open-drain, so you shouldn't have two outputs actively driving it. Disable one of the pull-ups. – Ignacio Vazquez-Abrams Jun 6 '13 at 14:33
• Irrespective of the motivation it is an interesting question that I have asked myself too. – Wouter van Ooijen Jun 6 '13 at 14:53
• Can you refer to a datasheet? – jippie Jun 9 '13 at 18:52

In the most abstract sense, what happens is this:

simulate this circuit – Schematic created using CircuitLab

You have a difference of 1.7V across 2.47 $k\Omega$, and so a current of about 0.69 mA flows from V2 to V1.

The line is not diven to a clearly defined state. On the left of R1, the level is whatever V1 is putting out. On the right, the voltage that of V2. Throughout the body of R1, there is a blend from V1 to V2. Obviously, this is probably not useful behavior for digital circuits where we want a defined logic level on a given signal line: the same level on both sides of any resistor.

The worst case current of about 2 mA occurs when V1 is driven low, and V2 is at 5V. From V2's perspective, it's just driving a 2.47 $k\Omega$ resistor to ground, but V1 has to sink the current. In the opposite case, V2 has to sink somewhat less current from V1.

• I understood the question to be "what happens inside the uC?" – user6972 Jun 10 '13 at 20:50

I don't think you'll find a spec on this. Some drivers can sink (and source) more current than others. Some are protected and some aren't. It depends on the types used by the die designers. To save money some versions of the same IC might have different drivers throughout its production cycles.

The 680uA current tries to sink into the VDD of the 1st uC. What happens depends on the type of output drivers on the die. Some drivers have some reverse voltage protection which feeds back to the supply of the circuity of the die some output drivers don't and can fail.

On a protected driver the current is shunted to the rest of the circuitry on the die. If it can not sink the excess current then it starts to raise the internal Vdd supply voltage. This can sometimes damage things unpredictably.

There are a few drivers that protect under both conditions where the internal circuitry is isolated and the driver is protected, however this is often not the case (follow patent trail on link to see more examples). Output drivers for pins take up a lot of die space and are often minimized.

• I agree with your opinion. However, I would like to know what happens on a lower-level. In this case, I am referring to an STM8L151R6 uC. The reference manual includes an I/O pin schematic, however, it doesn't detail on this scenario. If you check the quoted schematic you'll see the high-side mosfet (p-channel buffer). What I suspect to be happening is that the 680uA current described above is sinked throuh the high-side mosfet (through MOSFET's intrinsec diode - pn junction) to VDD. What's your opinion on this? – Nitro Jun 12 '13 at 9:06
• Section 9.3.6 shows they tested non-tolerant pins to +/- 5mA without any internal failures. However they also state "above VDD (for standard pins) should be avoided during normal product operation". I couldn't find the schematic you mention, but often they are simplified for publication. Call/email an STM application engineer. But in general if the specs say don't do it...as you noted the pn junctions are what usually get fried. If your 3V uC drives low it will sink even more current ~2mA. – user6972 Jun 12 '13 at 17:49