# Op-Amp oscillations when controlling P-MOSFET Vgs

My background is digital design, I guess the answer is obvious for all here, but not for me. I am studying example of analog physical layer for USB 2 protocol which I found in this paper. Also electrical scheme from this paper can be found here on page 92. I give the screenshot below for your convenience.

I implemented this scheme in MATLAB Simulink and find out that it generates oscillations. I deduced the part which is the culprit and again build it in Simulink. It is below with voltage-time diagrams.

From the simulations I see that the moment op-amp- input's value approaches op-amp+ input's value, it quickly overshoot desired value of 0.4 V and even goes negative instead of stabilize near 0.4 V (op-amp- potential). I suspect that the problem is in parasitic gate-drain capacitance of MOSFET but I do not know how to explain it. Also I thought that the problem is the fact that MOSFET starts closing with very fast speed when op-amp+ approaches desired value of 0.4 V. I tried changing parameters of op-amp, MOSFET, resistor. The picture differs, e.g. op-amp+ can do weaker overshoot and avoid negative voltage value, but nevertheless I always get oscillations: small, big, they are always here. The only way to avoid oscillation I found, is to make capacitance of MOSFET to be zero, which is not adequate. How can I avoid oscillations in the given scheme and what are their source?

• Many opamps will not drive a capacitive load directly on their output. What happens when you put a few ohms, or tens of ohms, between opamp output and FET gate? You may yet need a few 10s of pF from amp output to -ve input to 'speed up' the feedback loop you've 'slowed down' with the output to gate resistor. Commented Jul 4 at 10:23
• I tried 5,55,555,5555,55555Ohm. 55555 ohm makes oscillations disappear. (But op-amp+ is still not ideally equal to 0.4 V. It is 0.003V above, this is not a problem i guess.) I still do not comprehend why you advice helped to avoid oscillations? Commented Jul 4 at 10:32
• @converged_hyppo you are using a finite gain op-amp and that will create a static error. Try increasing the gain to some higher value and see what happens. Commented Jul 4 at 10:42
• @converged_hyppo it depends how faithful the opamp model is, and how faithfully circuit strays are modelled, a fed-back opamp, especially if there is excess capacitive load on the -ve input, tends to have an inductive-looking output impedance, which resonates with a capacitive load. The series R tends to 'de-Q' it, though 55k is far too much, should manage with <100 ohms if that is indeed the cause. The small speed-up C I mentioned is the mitigation for the effect of excess capacitance on the -ve input (some opamps advise removing ground plane underneath -ve input to reduce this capacitance). Commented Jul 4 at 12:48