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How can I calculate the sweep time of a PLL for a given bandwidth and a frequency span and setted step?
Let say:
Span 30MHz
Bandwidth 30KHz
Steps 200KHz

Edit:
So lets say we want to sweep from a start frequency A to a end frequency B where the difference between the two (the span) is equal to 30MHz, and we want to do that by step of 200KHz and at which the bandwidth is equal to 30KHz.
How much time will this/each (in case of repetable sweep) will take?

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  • \$\begingroup\$ Please show an example \$\endgroup\$
    – Voltage Spike
    Commented Jul 8 at 3:26

1 Answer 1

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The settling time to a new step is a rather strong function of minor design decisions like loop margin/order/stability, and the frequency accuracy you want when settled. It will be no quicker than 1/bandwidth, and could easily be an order of magnitude more than that. You will need to measure or simulate what it actually is, if you want a good estimate. Measuring it is a necessary first step anyway to improving it, if you find that it's slower than you need.

You have given a figure for step size, so presumably 'sweep' does not mean a continuous sweep, but movement across the span a step at a time. Different people will think of sweep speed differently, is it 90% of time dwelling on a step and 10% of the time slewing between steps, or some other figures?

Once you have a good figure for settling time, and a definition of what you mean by sweep, the sums involved in dividing the number of steps across your span by steps per second are trivial.

So lets say we want to sweep from a start frequency A to a end frequency B where the difference between the two (the span) is equal to 30MHz, and we want to do that by step of 200KHz and at which the bandwidth is equal to 30KHz. How much time will this/each (in case of repetable sweep) will take?

A 30 MHz span has 30/0.2 = 150 steps of 200 kHz across it.

That's the definite arithmetic done. Now we need to make some assumptions.

If the loop bandwidth is 30 kHz, then the fastest you can expect settling to a new frequency is of the order of 1/30k = 30 us. However, it could be rather longer than this, if the loop is not stable enough, or too stable. This time is to a rather undefined 'settled' specification of <1% of a frequency step. I have worked with synthesisers that specify a settling tolerance of sub-Hz, or even fractional radians from the final phase. These tighter specifications will increase the settling time. A settling time range of 30 us to 100 us seems handwavingly reasonable.

If you want to spend some time on frequency, then you will need a dwell time at the settled frequency, before making the next step. Perhaps 3x the step time, maybe 10x the step time. This makes the time range per step 100 us to 1 ms.

That finally gives you a sweep time of 15 ms to 150 ms, depending on the assumptions. You can always make the sweep time longer, with a longer dwell at each step.

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  • \$\begingroup\$ 6:35 => youtu.be/r8ofczZHt-g?feature=shared . \$\endgroup\$
    – Tintin
    Commented Jul 8 at 11:18
  • \$\begingroup\$ Neil please feel free to give a look at the edit in my post thank you. \$\endgroup\$
    – Tintin
    Commented Jul 8 at 13:26
  • \$\begingroup\$ Thank you Neil for replying and for the answer; so correct me if am wrong so the bandwidth it self is a sweep of frequency !! Because what i thought is band of frequencies generated at once or some sorte. So about the sweep time is ~ 30ų × 150= 4.5ms. \$\endgroup\$
    – Tintin
    Commented Jul 8 at 17:05
  • \$\begingroup\$ @Tintin If the bandwidth referred to in your question is the loop bandwidth of the PLL, then it means that the minimum time to settle a step is 30 us. So your theoretical 4.5 ms sweep is just counting the slewing time between steps, it never dwells on a frequency long enough for a measurement system to do anything useful with it. I'm not sure what you mean by the 'bandwidth itself is a sweep of frequency', it sounds like a misunderstanding on your part of what a PLL actually is. \$\endgroup\$
    – Neil_UK
    Commented Jul 8 at 18:19
  • \$\begingroup\$ Great explanation @Neil_UK ! I would like to add as an example that for a well-designed PLL, the 10 PPM settling time will exceed 10 loop time constants. So expect even slower performance. \$\endgroup\$
    – a360pilot
    Commented Jul 8 at 18:22

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