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Looking at the circuit below:

enter image description here

How do I analyze it? Specifically, why is the output able to go nearly all the way to +12 V but not beneath 0 V? I'd expect that when V(sig) < 0, since current flows from the PNP's emitter to its base, current should also flow from its collector to its base.

Looking at the graphs of the six currents (NPN/NPN, B/E/C), it's very hard for me to understand or predict the current flows.

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    \$\begingroup\$ Qpnp (reference designators - !) is upside down. \$\endgroup\$
    – AnalogKid
    Commented Jul 9 at 23:55
  • \$\begingroup\$ @SRobertJames I think you should have stopped at "Why the downvote?". The next sentence is pure speculation. The sentence in quotes would be a valid complaint if it were true. But we don't know that. To me the question looks perfectly fine. People seem to upvote the answers without thinking that hey, if the answer is worth something, then maybe, just maybe, the question that prompted is would be as well. \$\endgroup\$ Commented Jul 10 at 14:37

4 Answers 4

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But that's not a valid push-pull circuit to begin with.

You have the PNP transistor upside down.

Even if it were correct, for negative output you would need a negative supply and you don't have one.

Just like you need a positive 12V supply for positive output.

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  • \$\begingroup\$ Thanks. Can you elaborate on why the PNP has to have its emitter connected to the NPN's emitter and not ground? Either way seems to give similar results on LTspice, and both work much better than not having the PNP at all. \$\endgroup\$ Commented Jul 10 at 12:35
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    \$\begingroup\$ You are getting similar results because the transistor orientation is only one of the problems. The other one is that there is no negative voltage supply. PNP, NPN, right-side up, upside down - whatever -- no negative supply, no negative half-cycle output. \$\endgroup\$
    – AnalogKid
    Commented Jul 10 at 13:04
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Everyone has already pointed out that one of your transistors is arranged incorrectly. So I won't belabor it here. Sufficient that you know it won't work.

The phrase push-pull output also relates to quadrants (image borrowed from this Analog.com site):

four quadrant load diagram

With one end of the load tied to a fixed voltage, a push-pull output is attached to the other end of the load and works in two quadrants of the above diagram; quadrants I and III. In quadrant I the output is sourcing current in to the load. In quadrant III the output is sinking current out from the load.

A bipolar transistor can only do one of these things. It can't do both. So that's why at least two bipolar transistors are involved in a push-pull (2-quadrant) output.

There are, technically, four ways of combining pairs of bipolar transistors. PNPs may be used for both quadrants I and III, NPNs for both quadrants I and III, an NPN for quadrant I and a PNP for quadrant III, or a PNP for quadrant I and an NPN for quadrant III. Not all of these combinations make good sense. But they are all technically possible:

schematic

simulate this circuit – Schematic created using CircuitLab

In case A, if the two bases are separated by sufficient voltage difference (say about two diode drops' worth) then both transistors will be in active mode and the NPN can source current while the PNP can sink current. So this basic idea is often seen.

In case B, the difficulty is in driving both transistors, correctly, for analog use. Consequently, this kind of output stage is used more often when the output is digital. For the analog use, there will usually be two additional transistors added:

schematic

simulate this circuit

The above is just a behavioral illustration. (As are all the others above.) But with the addition of these two added transistors, and again so long as the two bases of the added transistors are separated by sufficient voltage difference (say about two diode drops' worth, again) then all transistors will be in active mode and the circuit can work as an analog output. This basic idea is also often seen.

Just for completeness, the digital case would look more like this:

schematic

simulate this circuit

C was (still is) used as a class-A digital output stage for the 7400 series TTL logic family:

schematic

simulate this circuit

And it can certainly also be used for class-A analog output as I illustrate here:

class-A amplifier example

Case D just isn't seen. Not in my experience, anyway. If you do see that arrangement in a practical circuit then you are seeing something rather rare.

That's about all I have to add here. Please become familiar with these behavioral topologies, and why they work.

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    \$\begingroup\$ C and D are equivalent, but since NPNs are usually better transistors than PNPs, there's nothing to gain by using the PNP-based D configuration. There's more configurations possible because for low-voltage power switching you may actually want the collector and emitter interchanged to lower the saturation voltage. So for each of the configurations you show, there's 3 more possible where one or both transistors are operating with reverse beta. Back in the 80s some large Japanese computer supplies used reverse beta switchers. IIRC they were synchronous, too. \$\endgroup\$ Commented Jul 10 at 14:44
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    \$\begingroup\$ @Kubahasn'tforgottenMonica Yes, I knew c and d were equivalent (considered saying so, in fact, but decided against it) and am aware of the rest, as well. Except for the first point, I wouldn't have been able to add the rest without having to completely change the focus. Nice to have you add this as a comment. :) Thanks! \$\endgroup\$ Commented Jul 10 at 21:26
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Each transistor is responsible for passing current in two different parts of the input/output waveform, between which current in the load changes direction.

The upper transistor is allowing current to flow from the positive supply, out of the output, through the load. This occurs on the positive portions of the input waveform.

The lower transistor passes current coming into the output from the load down to the negative supply, during the negative portions of the input waveform.

This requires that the transistors be chosen and orientated according to the direction of current through them, usually meaning that the upper and lower transistors are of opposite polarity (NPN vs PNP), and opposite orientation (emitter up or down):

schematic

simulate this circuit – Schematic created using CircuitLab

The arrow direction in those transistor symbols shows the direction of current within the transistor, which hints that your own (lower) transistor is upside-down.

Q1 deals with the situation where the output is positive in potential, and output current is to the right through load R1. During this period, Q2 is switched off and can be disregarded:

schematic

simulate this circuit

Q2 handles current coming in from the load, when output potential is negative, during which Q1 is off, and can be ignored:

schematic

simulate this circuit

We say that Q1 is a source of current, pushing current out, and Q2 is a current sink, pulling current in, giving rise to the term "push-pull".

It is possible to swap NPN and PNP, as long as we pay attention to current direction, ensuring that the arrows point the right way:

schematic

simulate this circuit

This arrangement is not common for analogue systems, for reasons too complex to cover here. The difference can be understood if you study "common-collector" (also called "emitter-follower") and "common-emitter".

The circuit at the top of this answer is common-collector, but this last circuit is common-emitter. They behave very differently, but both of these examples of "push-pull" pairs are valid, and their asymmetry is due to the different direction of load current during different portions of the input/output waveform.

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  • \$\begingroup\$ There are other ways to hook up pairs of transistors. Consider differential amplifiers. \$\endgroup\$
    – John Doty
    Commented Jul 10 at 19:15
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Your circuit is invalid. Try something like this. It can operate from a single-ended power supply. Reference the amp to 6-volts. Circuit reference https://circuitdigest.com/electronic-circuits/push-pull-amplifier-circuit-diagram

https://circuitdigest.com/electronic-circuits/push-pull-amplifier-circuit-diagram

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    \$\begingroup\$ R1 is not necessary, usually no current limiting is necessary for emitter followers, since base potential is not constrained by the base-emitter junction, as it would be for common-emitter. \$\endgroup\$ Commented Jul 10 at 3:58
  • \$\begingroup\$ Your circuit has the same problem as the OP - There is no negative voltage supply to the circuit. How do you expect to get an output of -3 V when the Q2 collector is tied to GND> \$\endgroup\$
    – AnalogKid
    Commented Jul 10 at 13:01

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