# I need help to identify the negative feedback loop in a hysteresis comparator

Can anyone help me identify where the negative feedback path is? I want to determine the feedback factors for both negative and positive feedback, but it's not clear to me where the negative feedback loop is.

The image is from this paper.

This is more details from CMOS Analog Circuit Design by Phillip E. Allen, Douglas R. Holberg.

• @MrGerber but my question is about the loop, what is the path or loop instead of a point.
– hana
Commented Jul 10 at 12:51
• ocw.mit.edu/courses/… Commented Jul 16 at 8:27

Suppose the comparator front end is at balance. You can simplify it as the drains both being connected to fixed voltages and the sources connected together to a current sink. At balance each transistor is conducting half the constant current $$\I_0\$$.

As V1 (gate voltage of M1) increase the proportion of current passing through M1 increases so the source voltage Vs will increase, which reduces the Vgs increase M1 sees.

At the balance point, the negative feedback is 50% (a 1uV change at the gate results in a 500nV change in Vgs).

• Hi, thanks for the answer. If we consier only half-circuit (M1, M3, M5), would there still exist negative feedback? It is a source follower to me and I don't see there is a negative feedback in it. For example, if V1 increases, then Vs increases at the same rate to make the tail current constant.
– hana
Commented Jul 15 at 5:42
• @hana yes, since in order to apply the analysis technique you allude to you should add a generator depending on v_i2 to the source of M1/drain of M5. In this way you can exploit the symmetry of the circuit and analyse it without neglecting important contributions. Commented Jul 16 at 8:14
• Hi, I think you misunderstood my question a bit. Consider a source follower with an ideal current source for biasing. If the gate voltage increases, the current will not increase (because of the ideal current source), but the source voltage will increase by the same amount to keep Vgs unchanged. This seems to contradict what you said above about V1, Id, and Vgs. Also, how would you get a 1µV change at the gate to result in a 500nV change in Vgs?
– hana
Commented Jul 17 at 5:59
• Because the source voltage increases by 500nV. Commented Jul 17 at 7:07
• @hana Why are you trying to do a half-circuit analysis when the image clearly states that the negative feedback is created by M1 and M2? You are absolutely correct that in the half circuit you created, you've removed the negative feedback (coming from M2). Commented Jul 17 at 22:51

Referring to feedback in this circuit may be confusing because the feedback is in the load of the differential pair. In contrast, textbook feedback examples have feedback from output to input.

First, consider that a pair of transistors in a differential circuit are functionally equivalent to a transconductance amplifier: voltage input controls a current output. This is a good model for the differential pair, M1 and M2, in your circuit.

simulate this circuit – Schematic created using CircuitLab

Now, consider the portion of the load of the differential pair consisting of M3 and M4. It looks similar to the differential pair, but the drains are connected to the gates. That is the same as connecting the output to the input of our model transconductance amplifier, as shown below.

simulate this circuit

So another perspective on a diode connected load is that it is a transconductance amplifier with unity negative feedback. The output impedance is $$\1/G_m\$$.

Now, we can consider the part of the load consisting of M6 and M7. It is almost the same, except that the feedback connections are crossed as shown below. This is where you get positive feedback, and the output impedance of this configuration is $$\-1/G_m\$$.

simulate this circuit

So all together, we have a transconductance amplifier (the differential pair) whose load is a transconductance amplifier with unity negative feedback (M3 and M4) in parallel with another transconductance amplifier with unity positive feedback (M6 and M7).

The balance of the negative impedance load and the positive impedance load determines the operation of the circuit: if the overall load impedance is negative it will be a latch and if the overall load impedance is positive it will be an amplifier (with high gain).

All of the discussion so far has been from the perspective of the differential-mode operation of the circuit. Every fully differential circuit supports a differential mode (DM) and common mode (CM). From a CM perspective, the transconductance of the diff. pair is much lower due to source-degeneration, and the load no longer has any positive feedback. You can find an explanation of this in any textbook describing a differential pair with a tail current source.

Lastly, I don't really understand what the quote from the paper is trying to say. The diff. pair only has negative feedback at the sources (i.e. source degeneration) in CM operation, but in that case, the load does not have any positive feedback. The load has positive feedback in DM operation, but in that case, the diff. pair does not have any negative feedback. So it is confusing that they say there is negative feedback in the diff. pair and positive feedback in the load—these 2 feedback paths do not exist in the same context.

• I think your answer makes more sense when you consider DM with two local negative feedback from M3, M4 and positive feedback from M6, M7 and CM negative feedback.
– hana
Commented Jul 19 at 7:12
• I took a look at the textbook section you referenced, and the circuit operation is explained with a single-ended input. In that case, the input is really 1/2 DM and 1/2 CM, so you do have negative feedback in terms of source degeneration for the CM portion of the input. I am not sure if that description would work for a differential signal path where the input had zero CM component. Commented Jul 19 at 17:44

If you look at a half circuit analysis, you're removing the negative feedback created by M2.

So you must look at both halves of the circuit together to understand the feedback path. This is simply a differential pair or a long-tail pair.

If you increase the voltage of Vg1, as a source follower, it tries to raise the voltage of the source by that same amount. But in doing so, it ends up pinching off some of the current from M2 because Vgs2 is shrinking. That lowers the overall current provided by M2. Now, M1 must provide more current than before due to the current sink below (M5). To provide more current, you must increase Vgs1. Therefore, a 1uV change in Vg1 doesn't increase Vs1 by an equal amount, but by a lesser amount. This is entirely due to M2 reacting to a change in Vg1. Remove M2 and you no longer have any negative feedback.

• You did a great job explaining the point. Do you know how to calculate the feedback factors for negative and positive feedbacks? The condition for hysteresis is positive feedback factor > negative feedback factor. And the result is (W/L) of M6 > (W/L) of M3. I don't know how to get this from feedback point of view.
– hana
Commented Jul 19 at 6:47

Can anyone help me identify where the negative feedback path is?

It's not really feedback in the conventional sense of amplifiers, as a comparator is an amplifier on steroids with a very high gain and a fast switching capability, they are more designed to switch from one state to the next than have a linear region like an opamp. One difference is opamps try to balance M1/M2 and comparators don't care, they want the voltage above M1/M2 to switch and turn off rapidly so the output stage can swing up and down.

It's really the current mirrors above M2/M1, redrawing the diagram with more ideal components and it would look something like this:

simulate this circuit – Schematic created using CircuitLab

But if you look at what is going on internally, it's described as feedback but I think that's a bad way to describe it as there are no conventional feedback paths, just current balancing with mirrors and current sinks and sources. It's better to look at where the current is going.

If you look at one of the pmos current mirrors, the current is blocked as one of the inputs becomes lower than the other. (look at M7/M4 red/blue combo on the bottom plot). This allows one of the M1/M2 transistors to recieve the majority of the current, which in turn sends the gates of M9/M8 in one direction or another (Green/light blue plot 2 toM8/toM9) and allows the back end to switch on and off and send the Vout signal flying to either one side or the other.

This differs from a normal amplifier because the region is a lot less linear and we aren't trying to balance M1/M2 sources that are assumed to be in a negative feedback configuration.