# Lattice Diamond PLL Configuration for decimal output

I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big fractional divider:

The equation I found from a Lattice guide online is: fOUT = fIN × N/M, which would make sense with what I have above (fIN =24, N=3, M=2, fOUT =36, and a tolerance of 5% would allow between 34.2-37.8MHz).

However, this causes a lot of jitter (>100ps), and so I need to find a work around.

I was thinking to make N=37 and M=24, which would give me fOUT=37MHz, but the software will not let me.

Is there a way to configure this that I am missing, maybe cascading multiple clocks? Should I create my own PLL separate from the built-in?

Thanks!

• What are the constraints on VCO frequency? One reference suggests 400-800 MHz, so a multipler of 17 and divider of 11 would give you a VCO frequency of 408 MHz and an output frequency of 37.091 MHz, which is off by only 0.095%. Commented Jul 10 at 19:01
• If you want to hit 37.125 MHz exactly, you'll need to cascade two PLLs. Set the first to multiply by 22 and divide by 8, giving a VCO frequency of 528 MHz and an output of 66 MHz. Set the second to multiply by 9 and divide by 16, putting its VCO at 594 MHz and the output at 37.125 MHz. Commented 21 hours ago
• @DaveTweed Thanks! I did try to do this, but the program is limited to one PLL, so I think we are looking into alternative solutions. I am still trying to understand why the software won't allow me to make the FBK divider = 37 and CLKI divider = 24. Commented 5 hours ago
• Because 24 MHz × 37 = 888 MHz, which is outside the range of the VCO. Did you try 17 and 11 as I suggested? Commented 4 hours ago
• @DaveTweed Yes I did, but it also throws an error saying "The Requested Frequency of CLKOP cannot be generated. Try changing the desired frequency or tolerance", but once you start changing the tolerance, it causes a lot of jitter. Commented 3 hours ago