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This is a question about the optimal routing for an STM minimal system. I made a minimal system board using the STM32H563VIT6. Is the routing method shown in the upper section, where I aim to connect to the pin header as shortly as possible, better, or is the routing in the lower section better? I want to open source it to make it easily accessible for those in need, so I aim to make it as perfect as possible. Please provide guidance.enter image description here

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  • \$\begingroup\$ I'm a beginner, and I want to use the minimal system I designed to learn the FOC algorithm. \$\endgroup\$ Commented Jul 11 at 9:48
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    \$\begingroup\$ Left side looks better than right side. All of them are likely functional. Conceptually. \$\endgroup\$
    – MrGerber
    Commented Jul 11 at 9:54
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    \$\begingroup\$ Please define "acceptable". There is no way to assess just the wiring, and there is very little to work on, like what each wire does, how much there is current, or does the PCB have 1, 2, 4, or more layers and how they are used, did you use impedance matching for any interface etc, or if the schematic design is even correct before you drew the PCB implementation. It looks like you copied the same USB-C CC pin error from Raspberry Pi like everyone else, which is sort of interesting phenomenon itself. The pinheaders with GPIO only are rather useless without power or ground pins for example. \$\endgroup\$
    – Justme
    Commented Jul 11 at 10:13
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    \$\begingroup\$ You really shouldn't do this with just 2 layers. \$\endgroup\$
    – Lundin
    Commented Jul 11 at 10:37
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    \$\begingroup\$ Just my opinion: perfection here will be elusive, because you have no idea what other people would use the board for. There are a lot of the usual comments about signal integrity, but it's based on a guess of what the pins might be used for. As a basic board to do simple prototyping, it seems fine: go ahead and make one and see how it goes. \$\endgroup\$
    – Smith
    Commented Jul 11 at 14:11

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I'd call the differences between the top and bottom half routing rather cosmetical and irrelevant.

What matters here would be two things:

  1. Conceptional fitness for your purpose
  2. Signal quality and EMI aspects

Conceptional Fitness for a Purpose

So, you've designed another breakout board for an STM32 IC! That's an excellent exercise, especially because with the existing Nucleo-H5xxx boards, there's bound to be an example layout.

Now, whether an existing board or your own board fits your needs is impossible to tell without knowing what these needs are. Primarily here, the question is what you plan to attach to these GPIO headers. Is it going to be external switches, actuated slowly by humans? OK, you'll get away with basically any trace layout. Is it going to be external RAM, or a high-speed bus, or the hilariously-named "Octo-SPI" (that's a parallel bus, yo, ST)? You better make sure you have a directly adjacent plane on which the return currents can flow, uninterrupted. Are you going to drive an external MOSFET at a high PWM rate? You might want to also keep that trace away from sensitive signals. (1)

So, requirements first, board layout after. Just simply exposing all pins to a pin header doesn't mean every functionality can be usefully employed. A board that supports a definite subset of the functionality of an MCU well is worth more to the user than a board that does a lot, but a lot of it in bad ways.

For example, you have more than 80 signals on pin headers (I guess 2.54mm pitch), > 40 on each side. Who is going to use them and how? Again, lots of high-speed peripherals on that IC, questionable choice of connector for these. Is this targetting being plugged into solderless breadboard? Then, this is very useless: you can't do anything with a pin in the middle of these 10 cm of contiguously used breadboard rows: you'd need to "escape" 5 cm to the side to do any more than connect that pin to ground or VCC. At that point, you made a complex board to carry all the MCU pins to external pins – that you can't really use. (and, see signal considerations below on why you would need even more pins, acshually.) If this is meant to be a base board into which you plug other boards, then it strikes me as a rather inelegant shape – make it more square than elongated, and you get shorter traces, you can route around the pin headers if they're not at the very edge of things (see "two layers" below), removing the connection is more likely to work with out bending pins…

There's one thing I see immediately: there's a resistor next to your USB connector – probably the 5.1 kΩ for detection. But these should be two, not one, and you mustn't connect CC1 and CC2 directly! The whole point of plurality of these pins is to allow for orientation detection by smart cables and chargers. You cannot just short them and hope your device would still work with an electrically marked cable! It raises the question where you got the idea from – I checked the openly available (not open source by the actual meaning of the word) schematics of the Nucleo-H533RE board, and it doesn't make that mistake. Also, if this is a general purpose board, you'll hate yourself if you saved the ~ 20ct for a USB TVS diode pair IC and then end up frying your microcontroller through the USB data lines. So, TVS diodes: your friend, cheap. Use them.

Signal Quality and EMI Aspects

So, from (1) arises my only question that is independent from your usage: did you make sure that every signal you export has a current return path? Meaning: is under each trace on the top layer a ground trace parallel to it, or simply a ground plane, which goes from external pin to IC pin? Otherwise, you'll have signal energy travelling where you don't expect it to. It might work, it might not, it might drastically reduce analog performance…

In general, if you have an external connector and are connecting to some higher-speed interface on the chip, I'd expect that the external connector puts a ground (or more specifically, reference potential, but that's going to be ground in your context) pin next to it. You don't do that – so that these pins will mostly be useless for highspeed signals. Remember that the signal energy isn't carried by the conductor – it's carried by the electric field between the conductor and its reference plane. So, you really want to define the place where that field mostly exists well, so that the places of different signals don't overlap. That, in a very slight generalization, means that on a PCB, you always want to have a ground plane beneath your signal path. And you mustn't interrupt that, e.g. with a different signal or power trace running on the same layer as the ground. (It doesn't have to be a full layer plane, but it needs to be high-frequency contiguous.)

So, looking at the top side layout, I can't really judge, but there's hints that this is supposed to be a two-layer board. That can't work for high-speed: the top layer is "blocked" by the traces going to the pins, so all remaining signals need to cross the bottom layer – which you need as contiguous ground beneath the external signals.

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