Does DDR3 master clock need to be longest trace in general?

Question

I'm working on my first PCB which incorporates DDR3L memory with an STM32MP157AAB3 processor. I've been following ST's DDR3 guide from AN5122 and I came across something which I found odd and which my current layout violates. In section 6.2, it states:

Length of DQS_N/DQS_P must be from 0 to 590 mils (14.986 mm) shorter than CLK_N / CLK_P length (CLK_N/CLK_P must be the longest traces).

Is this a general rule for DDR3 routing? My understanding was that all address/commands signals are clocked by CLK_N/CLK_P and each byte lane is clocked with DQS_N/DQS_P which would make me think the relative length between these two clocks shouldn't matter? I'm working with only four layers so space is pretty tight and I'm not sure I can shrink DQS signals or alternatively lengthen the CLK signal.

Would it be a bad idea to ignore this rule?

Answer 1

Section 3.4 PHY tuning of AN5168 How to configure DDR on STM32MP1 MPUs contains:

It is expected that the DQ and DQS from all byte lanes arrive at DDRPHYC well aligned. The recommendations provided in the application note AN5122 [5] help to ensure matched delay paths on the PCB. Consequently, the fine step delays, provisioned in the DDRPHYC, do not need to be modified and can be left at their default values.

Looking at RM0436 Reference manual STM32MP157 advanced Arm ® -based 32-bit MPUs in section 7.4.3 Interface timing modules (ITMs) of the DDR physical interface control (DDRPHYC) chapter there are mentions of:

• Fine step delay
• dqs_trm[2:0]: delay dqs/dqsb in -3 to +4 fine step

However, I can't seem to find a detailed description of how to use the fine step delays in the DDRPHYC registers. The RM0436 chapter about the DDRPHYC starts with the following, which suggests that STM used Synopsys IP for the DDR controller:

Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission.

This isn't a definitive answer, but it looks like:

• If the PCB layout doesn't match the length constraints in AN5122 then the software may need to adjust the fine step delays in the DDR controller registers.
• However, it isn't immediately clear how you determine what to set the fine step delays to accommodate the PCB trace lengths.

STM DDR controller Terminology

From a comment:

Delay equalization (a.k.a. "write leveling" and "read leveling") is done on each power up, by sweeping through the delay values to find the edges of the data "eye", and then setting the final delay to its center. Some DDR controllers have this built right into their internal state machine; others require a software routine, normally supplied by the vendor. – Dave Tweed

Looking at the STM32MP1 documentation I can't seem to find the terms "write leveling" and "read leveling" used. AN5168 How to configure DDR on STM32MP1 MPUs mentions Built-in DQS gate training (DQSTRN) and read valid training (RVTRN) as part of the initialization sequence. I.e. think DQSTRN and RVTRN could be the equivalent STM terms for "write leveling" and "read leveling".