# The role of Q33 and the connection of pre-discharge circuit in the BMS circuit

I'm trying to understand the following circuit which is taken from the TI's TIDA-010216: I don't understand the role of Q19, D29, D30 and Q33 in the circuit. According to this post, it seems that Q19, D29 and D30 are used in order to prevent OUTA pin from PACK- negative swings but I'm not sure about that. Also the role of Q33 is still unknown to me.

The other problem is related to the pre-discharge circuit. According to the block diagram of the TIDA-010216, current-limiting resistors R118 and R119 should be connected to the PACK-, which is reasonable to me, but in the provided schematic that's not the case: Edit: I think this post and this picture answer the second question:

When the charger is a simple CC-CV source and does not know or pay attention to what the battery voltage, the battery may implement a pre-charge circuit to reduce the charge current while battery cell voltages are below a set threshold. The pre-charge current can flow through the discharge FET body diode or through the main FET path if the discharge FET is turned on.

## 1 Answer

Here is where the circuit in question lies in relation to the over-all system:

Figure 1 (Above).
Link for above image:
https://www.ti.com/lit/df/tidmb13/tidmb13.pdf?ts=1721547693534

The two MOSFETs form a switch between the nodes [BAT-] & [PACK-]. When both MOSFETs are OFF, the switch is open meaning no current flows, and the voltage at [PACK-] may differ from the voltage at [BAT-]. If both MOSFETs are ON, then the switch is closed, the two nodes are at the same voltage, and current may flow between them in either direction. If only one MOSFET is ON, then the current may only flow in one direction, depending on which MOSFET is ON and which is OFF. If current is flowing then the two nodes are at the same voltage, otherwise if current is not flowing then it is possible for there to be a voltage across the two nodes. This is explained in the image below:

Figure 2 (Above).
Link for above image: Page 8 of https://www.ti.com/lit/ml/slyp856/slyp856.pdf

The problem is that the circuit (chip) used to drive the gate of the MOSFETs is sensitive to negative voltages at its output pins. This chip is the UCC27524, and the explanation in the link you provided (to the ti support page) is correct, specifically this section:

Special precautions must be taken to prevent PACK- negative swings from reaching OUTx pins as the UCC27524 will not handle negative voltages exceeding -3V.

The circuit works as follows: if node [CHG] is low (0V wrt GND) then Q27 is OFF, and Q5 is also OFF (Q5 Vgs is 0V). If node [PACK-] goes negative, then Q5 S-pin follows it, and so does Q5 G-pin (since Q5 has a large capacitance between G & S pins). Q27 pin D also follows this negative voltage (it is connected to Q5 G-pin). However, Q27 is OFF so this voltage does not propagate to Q27 pin S. Q27 D-pin voltage will go more negative than its G-pin, which is OK since it is a P-chan device.

However, the circuit presented in that link is not quite the same as the circuit in question (the circuit given in the TI product code TIDA-010216). Note: I have added a wire to show the connection between the two nodes marked [CHG_D]. The similarities are listed below (ckt in link at left, circuit in question at right):

1. Q27 ==> Q19.
2. Q5 ==> Q30, in parallel with Q29, Q28, Q27, Q26.
3. [CHG] ==> [U5 OUTA].

The differences are highlighted in the image below, specifically, the following components have been added:
R110, D29, D30, R122 (& the 4 Rs to the gates of the other MOSFETs in parallel with Q30), D33, R127, Q33, R131, R134.

Figure 4 (Above).
Link for above image: Sheet 4 of the schematic:
https://www.ti.com/lit/df/tidmb13/tidmb13.pdf

The additional components can be explained as follows:

1. R110, R122. There were mentioned in the link to the TI support page (these slow-down the operation of the switch).
2. D29, D30: These protect U5 from positive voltages at [PACK-]. They also provide a means to reduce power dissipation (hence reduce battery drain), refer point 4 below.
3. R134 is a 1k load at the output of U5 OUTA via Q19 & D29.
4. Q33, R131: these turn off the main switch by providing a discharge path for gate-source capacitance of the main MOSFETs (Q26, Q27, Q28, Q29, Q30). This discharge only occurs when U5 OUTA is low; this reverse biases D29, which turns on Q33 via R134, which then becomes a self-sustaining current until Q33 emitter voltage falls to ~0.7V above its collector voltage. Note that Q33 is kept OFF while U5 OUTA is HIGH, since its emitter is more negative than its base. This helps to reduce the power supply current, since this circuit is powered from the battery, & we want to minimise battery discharge.
5. D33 (zener) protects MOSFET gates from over-voltage.
6. R127 provides a slow-discharge path to keep MOSFETs off when the circuit is not active (ie: when no battery is connected to the circuit).
• Thanks for the answer. Would you explain how D29 and D30 protect U5 from positive voltages at [PACK-]? Also if Q33 and R131 are used for discharging the charge FETs, why is there no discharge path for the discharge FETs (Q21, Q22, Q23, Q24 and Q25)? I don't understand this asymmetry in the design. Commented Jul 21 at 11:13
• **Q1. Would you explain how D29 and D30 protect U5 from positive voltages at [PACK-]? ** ANS: Consider the case where both main MOSFETs are off, and U5 OUTA and OUTB are both low. If [PACK-] goes positive wrt GND, then D33 (zener) is forward biased causing D30 cathode to go positive. Also, D29 cathode goes positive via R134. So D29 is reversed biased, it blocks positive voltage from reaching U5. Commented Jul 21 at 13:45
• **Q2. why is there no discharge path for the discharge FETs (Q21, Q22, Q23, Q24 and Q25)? ** ANS: Because there is no diode blocking the gate discharge path for these MOSFETs. U5 OUTB (a low-impedance output of a gate driver) is free to both charge (turn on) and discharge (turn off) the main MOSFETs (Q21, etc). But U5 OUTA cannot turn off its MOSFETs because of D29. The asymmetry exists because the MOSFETs are not connected the same way; the discharge MOSFETs (Q21, etc) have sources connected to GND; whereas the charge MOSFETs (Q26 etc) have sources connected to [PACK-]. Commented Jul 21 at 14:03
• Thanks for the responses. Here is my understanding, I would appreciate your feedback: Suppose that Q19, D29, D30, Q33, R131 and R134 are removed and R110 is connected directly to [PACK-]. When the main FETs are off, we have no control over [PACK-] and it can have positive or negative voltage wrt GND. So OUTA can have positive or negative voltage wrt GND such that its maximum ratings are exceeded. For solving this issue, we first add D29 and D30. In this way, positive voltage only turns on D33 and can't reach OUTA. Commented Jul 21 at 19:03
• Q3: Why two diodes D29 & D30, not just one diode? ANS: Imagine D30 was removed by shorting it. D29 still protects U5 from positive voltage, however, the problem is that Q33 cannot assist the turn off since its base is shorted to its emitter. So D30 allows Q33 to help speed up the turn-off of Q26 to Q30. Now imagine D29 is removed by shorting it. [PACK-] can now reach U5 via R134. Commented Jul 21 at 23:34