# How to decide sizes for transistors in a design? What does it mean to design an IC?

I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. I also try to design them in the open source PDKs (SKY130, GF180, FreePDK etc.) when I have some free time.

I am not even sure that what I do can be called designing these circuits. Since textbooks don't mention sizes or any ratio for the relative sizes of NMOS-es and PMOS-es or any other way to systematically figure out the proper size, I start with an initial guess and then I have to do a lot of trial and error to find a size that is working.

Since I am unaware of any systematic way to figure out sizes for my circuits or something more solid than trial and error, I am not even sure if the size that I got by trial and error is the most optimal size for the circuit. And it is not as if the behavior of all the circuits varies linearly with size i.e. for some circuits I have seen I would get good performance at say 4u/60n but then for the same circuit, the performance would be severly degraded for anything larger than that.

I have asked other more experienced senior students and they have told me not to rely on too much rigorous math or methods to design circuits. But to me, it seems designing a circuit is first reviewing all the available topologies and then implementing them with some modifications to achieve a desired function, and if I don't figure out the size of the transistors, even a theoretically sound topology doesn't seem to work. Take for example, this VCO I was recently trying to design in a TSMC 65 nm process and the same topology in SKY 130 nm process. I was able to figure out the right size in the latter process after 2-3 trial and error attempts but in the former, I still haven't been able to make the circuit function.

This is not just a problem, I am facing with one circuit, it is with all of them.

If anybody could please help me out on how I should approach designing circuits, it would be highly appreciated. Since I know of no systematic approach as to how a specific size works I feel like I have no insight into the circuit's behavior i.e. if I want to further optimize it, I feel like that is not possible.

Also what else is there, in designing a circuit besides choosing a topology and making it work and optimising it? Am I missing something? Any and all advice would be appreciated, I am just starting out in actually trying to design my circuits and I feel completely frustrated, as I am not able to make any circuit work due to improper sizes.

It sounds like you are trying to operate on too many levels of the technology stack at the same time.

Systematic design usually starts at the circuit theory level. You draw a schematic, and for the transistors specify gains, maximum capacitances, minimum fts of the generic transistors, to get the circuit to work in simulation producing a specified circuit performance.

Then you set about implementing the transistors in terms of choice of process and geometry, to meet the individual transistor gain and ft specifications.

No human has the mental bandwidth to be able to design circuits without this intermediate step. If it turns out that this two-step process doesn't produce a circuit working to specification, then you go back and improve the modelling of the transistors at the schematic/simulation level, not poke around with the transistor geometries directly. Usually any 3rd party published process will already have excellent behavioural models for use at the circuit theory level simulation.

It's rather like the use of compilers. No programmer writes a high level application in machine code these days. If it turns out that the compiler doesn't produce tight enough code, you go back and play with the compiler flags, or switch compiler, rather than hack the machine code directly.

And the rare edge cases where this general advice doesn't hold are precisely similar in IC design and programming domains.

• I would expect that especially in the early days of ICs, many devices came about by evaluating what characteristics were achievable in silicon, and then figuring out how to use them. Probably less need for that nowadays. As for compilers, if part of my code can't satisfy performance requirements in C, I would rewrite that part of the program in assembly language long before I'd think of monkeying with the compiler, though I wonder if maintainers of some free compilers might have favored the latter approach, to the detriment of reliability. Commented Jul 23 at 19:40

The base is to have an intuition about what the sizes do to the transfers and parasitics of your circuit.

Here's a very simple example: sizing the 1st stage of an Op-Amp feedback amplifier. I don't know if all designers size it in this way, but I was taught like to his by damn smart ones.

One assumption you can make for the 1st stage is that it dominates the noise performance of your amplifier. As such, you can simply choose an input topology (some sort of differential amplifier, most likely) while the 2nd and subsequent stage can be abstracted away by a VCCS or VCVS with some gain on it. As long as there's loop gain in the whole feedback loop, you can simply simulate noise by sweeping the bias current of the stage. That'll give you the optimum noise for your choice of sizing.

Most likely, you need a lot gm in the input stage in order to suppress more noise from subsequent stages, as well as to reduce the 1st stage own current noise contribution (with obvious diminishing returns the bigger the stage is).

These are the kind reasoning you must place whenever you're about to size something. Even using small signal analysis could help you determine what is it you need to meet the specs. Then choose a topology and size it in order to meet that gm or ro you need. For that you'll need to characterize your transistors, or use an optimizer.