# How important is a "no reflection" strategy for 1 Hz systems?

One of my colleagues claims that no matter what frequency the PCB board has, you cannot allow reflections inside the tracks. In this case, it's 1 Hz frequency that is going to turn a relay ON. The control signal to the relay is controlled by one AND-gate and followed by two OR-gates.

He claims that I need to study the reflection between the AND-gate and the OR-gates. He suggests that I should have a resistor between these two gates, to prevent reflections.

I said that it's no speed. And he said that it does not matter. What he said is the rise time that matters. If the rise time is to small, then the system won't work at all, no matter how "slow" the system is or what type of impedance the inputs have.

The relay is going to be turned on constantly, and sometimes the relay is going to act like PWM in 1 Hz.

Question:

What's the idea by having a serial termination between two different gates, if the PCB board is not high speed? According to him, the PCB would not even pass the test if I don't have some kind of termination that prevents reflections and he repeats that "High speed or low speed or 1 Hz...you need to compute the rise time and compute what type of serial resistor you should use to prevent reflections".

So now I'm confused. How can a well experienced engineer (masters degree) claim that? It must be something he has noticed that nobody else has noticed?
Like a pit fall?

Some further details added in comments (now chatroom) which may be relevant:

It's 50 mm between the gate inputs/outputs. [My colleague] claims that it could be reflections there.

There is a "clock" signal that comes from a 555 timer of 1 Hz. He claims that the output must have a serial resistor, if the rise time is to low. He claims that the input of the AND-gate might missunderstanding the input signal from the 555 timer. The distance between the 555 and AND is about 50 mm.

The AND gate is 74LVC1G386GW and the 555 timer is LM555CMMX/NOPB and the OR gate is MC74VHC1GT32DFT1G.

• @All - Although well-intentioned, the long comment chain has exceeded what is reasonable for comments. Therefore comments so far have been moved to chat & should be continued there (see link in the comment below). || As this bulk moving of comments to chat can only be done once per question, any further comments posted here may be deleted without notice. Keep it in chat now, please! || Answers can still be posted, as usual. TY Commented Aug 9 at 19:37
• Comments have been moved to this chatroom and discussion should be continued there. Please do not continue the discussion in comments here. Commented Aug 9 at 19:38
• "sometimes the relay is going to act like PWM in 1 Hz." As well as the termination issues already discussed you should check the relay rating for number of switching operations and see how long your planned PWM usage will take to run through that rating. You may need to use electronic switching for PWM. Commented Aug 10 at 10:03

Reflections depend on edge rate and required signal quality; and any extenuating circumstances, like if slow edges cause excessive power dissipation or chattering/oscillation of logic gate inputs, or increased sensitivity to induced noise; or peak overshoot activates ESD diodes, causing unexpected current flows and aberrant behavior; or if resonances on traces or power pins cause excessive EM emissions.

Reflections do not depend on repeat rate. It's the edge itself that's doing the reflecting. The repeat rate, or clock or data rate, is just how often an edge [or two] occurs.

A relay, needless to say, is a dumb pile of wire and metal. Signal quality is irrelevant there, and your colleague is being wildly overzealous.

They might still have a point, with respect to the driving gate's output pin, and what transient current it sees driving an otherwise unterminated stub trace. (Relay coils have high impedance at high frequencies, so the far end of that trace won't have much impedance shunting it.) Perhaps the ringing affects EMC as well (but if the toggle rate is truly ~Hz, this seems unlikely; it could be more probable with a fast/power-saving coil driver, that applies high voltage initially then after a moment, drives PWM to maintain holding current).

If the gates are adjacent, the trace between them probably has no signal quality issues. Mind, this is relative to the speed of the signals in question. Families are available from slow-as-molasses to literal light-speed. CD4000 basically never needs termination (but that's mainly because its output impedance is too high to drive typical transmission lines). The fastest standard logic available, in PECL or CML, have edge rates in the 10s of ps, where essentially any trace length on a PCB has to be treated as a transmission line. Using 74VHC, LVC or thereabouts, the edge rate of one or a few ns, which is safe to use without termination for trace lengths up to 10 cm.

LM555 is slow, on the order of CD4000, though it is strong enough to drive transmission lines, so would eventually have some concern (i.e. in the 10s of m range). More to the point, the output pin doesn't pull very far up, so if you're running everything from +5V, the logic gates probably aren't seeing full input levels (VIH). I would urge using 74HCT gates here.

It's possible your colleague knows more about your design -- things which have not been communicated here. Without a schematic, layout, etc., we can only speculate. I will note that 'LVC386 is a three-input XOR, not an AND, which seems... problematic?

To summarize, it appears both of you are right and wrong, in differing directions. Your colleague may be omitting (or forgetting) assumptions they have internalized on the topic. When one works on a given topic, deep enough and for long enough, many things can become taken for granted; gently remind, or probe into, these assumptions, and see if you can get a more nuanced or general perspective that applies to your design.

Likewise, avoid talking in circles: don't create a "but what about X!" "but I'm doing Y!" situation: rather, drill down into both X and Y until it becomes clear which details apply to the problem in question, and which do not. For example: what logic family, what edge rate, what trace length, what signal environment (is this microstrip over ground plane, or what?), etc.

Cheers!

• In the comment the OP mentions its 74VHC and 74LVC logic that triggered the question, both of which are faster than 74HC, so could that be part of the concern? Commented Aug 9 at 19:36
• The point is, when you're driving a relay, neither the speed nor the cleanliness of the signal edges matters at all. Commented Aug 9 at 19:41
• @DaveTweed The relay may not care. Or the transistor between logic gate and relay. The logic gates however do care and you want them to work properly. E.g the LVC1G386 requires input slew of 10..20 ns/V, and the output can have down to 1ns slew rate - required bandwidth is approx 350 MHz. Commented Aug 9 at 19:54
• @user1937198 The broader truth is to simply understand that "high speed" is what a circuit does, not some label you arbitrarily ascribe to it. If you need to take account of transmission-line effects, because the rise time is shorter than the electrical length of the traces, or other effects, then that is what you must do. Without a layout given, or requirements or other specs, I can't make any further assumptions (at least short of building a book-length answer), but I can direct the reader to what relative quantities are important. Commented Aug 9 at 20:02
• Case in point, maybe 74HC doesn't care about 10s-cm trace lengths. VHC and LVC might care about 10 cm length or shorter. It's all relative. Check the datasheet and appnotes for specifics. Commented Aug 9 at 20:03

The big takeway is that you are using "fast" chips so you have a "fast" design. The fact that the signals through the fast system are 1 Hz signals is irrelevant, because fast chips have fast outputs and they require fast inputs even for 1 Hz signals.

The VHC logic IC needs input slew rate of 10ns per volt for a 3.3V logic signal and the output rise/fall times are 3ns - the output signal edges have 116 MHz bandwidth. If the input is slower than required, the output may oscillate when input is near the threshold and does not cross the threshold fast enough. The input thus needs to be fast enough to change 3.3V in 33ns - the input signal bandwidth must then be more than 10 MHz, no matter how long period there is between the edges.

The LVC logic IC is even faster. It also requires 10ns per volt input signal slew, but the output slew rate is less than 2.5ns at 3.3V - a bandwidth of 140 MHz.

The LM555 has 100ns rise/fall times. The output changes slower than required by the VHC and LVC chips.

Also your PCB wire design then needs to pass these fast edges. If it does not, it acts as a low pass filter, and then fast square edges begin to have undershoot, overshoot, and oscillation for each transition.

PCB wires are not 0 ohm superconductors, they have small resitance in milliohms, but more importantly, each infinitely small length of copper trace has inductance and capacitance, hence it is a transmission line with some impedance.

This is not RF quite yet, but relevant to signal integrity for fast digital signal. Applying a rule of thumb, a signal edge with 2.5ns transition is 50cm long, assuming the signal travels at two thirds of the speed of light in the wire. Thus any wire longer than 5cm must be considered as a transmission line and signals start to reflect off at impedance mismatch points, i.e. at the transmitting chip and receiving chip. Same thing as waves traveling in a swimming pool, they reflect back off the pool wall when they hit it.

The sent signal going forward and the reflecting signals going backward sum up, leading to these overshoots, undershoots and ringing at each edge.

To combat these reflections, a typical solution is to limit the slew rate a bit with a series resistor on output.

As it happens, this is exactly the same thing as hobbyists using too modern and fast chips to fix old equipment or trying to use too modern and fast chips on extremely poor environment like on a breadboard. Old slow chips have no problems working in slow environment with other slow chips, but new fast chips do not work correctly in slow environment with slow chips.

So, in short, your 1 Hz signal through fast chips coud be an RF oscillator emitting a bust of electromagnetic interference each time the 1 Hz signal toggles, unless the design is made propely, i.e. all the chips are used within rated operating conditions regarding their input and output signal requirements, which includes bypass caps at power supply pins.

FWIW, TI's rule-of-thumb for LVC logic is you don't need to add resistors if the traces are less than 4", so the 50mm is well within that limit, even ignoring the fact it's slow-as-molasses combinatorial logic. See 1-27 in the above-linked document:

Proper Termination of Outputs

Depending on the trace length, special consideration may need to be given to the termination of the outputs. As a general rule, if the trace length is less than four inches, no additional components are necessary to achieve proper termination. If the trace length is greater than four inches, reflections begin to appear on the line and the system may appear noisy and generate unreliable data. The solution to this is to terminate the outputs in an appropriate manner to minimize the reflections.