# Determing the line and load regulation of a Zener MOSFET regulator

I am working on a circuit involving a bridge rectifier, a smoothing capacitor, and a Zener-MOSFET regulator. I need help finding a mathematical representation of line regulation and load regulation of this circuit (ignoring parameters like temperature). Here is the overall circuit diagram:

I have created a small-signal model of the regulator to isolate the output voltage ($$\v_o\$$) in terms of the input voltage ($$\v_i\$$). The small-signal model looks like this:

Using this model, I derived the following expression for $$\v_o\$$: $$v_o=v_i\frac{\left[g_mR_L(\frac{r_z}{r_z+R_R})+\frac{R_L}{r_o}\right]}{1+\frac{R_L}{r_o}}$$

Here, $$\g_m\$$ is the transconductance, $$\r_z\$$ is the Zener resistance, $$\R_R\$$ is the resistance in series with the Zener diode, $$\R_L\$$ is the load resistance, and $$\r_o\$$ is the output resistance of the MOSFET.

My questions are:

1. Am I on the right track in using this small-signal model to determine the line regulation? I am unsure if the derived expression represents line regulation or just a small-signal representation of the ripple voltage.

2. How can I use this small-signal model to find the load regulation?

Any guidance or suggestions on how to proceed would be greatly appreciated!

Thank you!

• Depending on your line voltage range, real-world line regulation is going to have a significant impact from the change in temperature of the zener with line voltage. (You can get close to zero tempco by picking the right zener voltage, or combining zeners.) Commented Aug 11 at 17:53
• Hi John, thank you for the insight, I've updated my post to be a bit more clear on what I am trying to solve. Specifically, I am interested in a mathematical representation ignoring things like temperature. I should have been more clear, my apologies! Commented Aug 11 at 17:56
• Also, the FET operating point and gm will change with line, so small-signal analysis on its own may not be accurate. Commented Aug 11 at 17:57
• The fundamental issue is open loop then required V drop to lower Zout then Vgs tolerance is 50%. Only a PFET works better with high gain error amp on Vg. We must learn all the fundamental weaknesses of components then choose specs before we can design. Then verify by lab test or simulation and compare with math. Commented Aug 11 at 19:31
• Expect to make lots of errors in choices as we learn what works and what doesn't. Don't give up trying, just verify assumptions. Commented Aug 11 at 19:38

How can I use this small-signal model to find the load regulation?

Load regulation is the expected (and hopefully maximum) change in output voltage corresponding to a specified change in output current. For example in a LDO datasheet you may find "Load regulation: max 1% change in output voltage between minimum and maximum load".

So, first you need a variable output current in your model: either two different values for the load resistor, compute output voltage for both, and take the difference... or use a current source instead of the load resistor, and compute Vout(Iout).

Then, the small signal characteristics of the MOSFET (and especially gm) strongly depend on load current. So the small signal model at a certain operating point (Vin,Iout) will give you output impedance at this output current.

Load regulation is inherently a large signal measurement, so you cannot use a small signal model linearized at one output current to calculate it. You'd need to calculate the operating point on both ends of the range, and take the difference in output voltage.

Am I on the right track in using this small-signal model to determine the line regulation?

Same as above:

You can use a small signal model at a certain operating point (Vin, Iout) to get PSRR, which compares a small change in input voltage to the corresponding change in output voltage.

But for line regulation the small signal model will only work if the input voltage range over which you want to measure line regulation is small enough that the small signal model remains accurate, so... the result is PSRR, not load regulation.

In addition, usually these two measurements take into account heating of the device due to higher voltage or current. For example inside a LDO the voltage reference, error amp, etc, are on the chip next to the pass device which heats them, thus their drift vs temperature influences the result.

In your MOSFET regulator case, you'd also have to take this into account.

• Thank you bob, this is extremely helpful for me to test out in LTSpice as I think at this point I can simulate both the line and load regulation without issues. The problem still remains, though, how do I mathematically represent the load regulation then? (Since I can't use the small signal model) Commented Aug 11 at 18:59
• To do it mathematically you'd have to calculate the operating point, you can do that with the equation of Id as a function of Vgs. But if you want to take channel length modulation (MOSFET Early effect) into account then... it's much simpler to use the simulator... Commented Aug 11 at 21:09

Small-signal analysis explicitly ignores the significant changes in operating point of the transistor. When operating in the source-follower configuration, $$\V_{GS}\$$ has strong dependencies on both $$\I_D\$$ and temperature. Just take a look at Figure 7.2 of the SSM6K818R datasheet. Even if you regulate the gate voltage perfectly, your load regulation will be terrible. If you want to use a MOSFET as your control element, you need to have voltage feedback from the actual output node.

This answer is using AI and i feel it is correct

1. Line Regulation The expression you derived for ( v_o ) in terms of ( v_i ) is indeed a small-signal representation. To determine line regulation, you need to analyze how the output voltage ( v_o ) changes with variations in the input voltage ( v_i ). Line regulation can be found by differentiating your expression with respect to ( v_i ): ∂vi​∂vo​​=[1+RL​ro​gm​RL​(rz​+RR​)+RL​ro​​] This derivative gives you the sensitivity of the output voltage to changes in the input voltage, which is directly related to line regulation.
2. Load Regulation To find load regulation using your small-signal model, you need to analyze how the output voltage ( v_o ) changes with variations in the load resistance ( R_L ). You can differentiate your expression with respect to ( R_L ): ∂RL​∂vo​​=vi​[(1+RL​ro​)2gm​(rz​+RR​)+ro​​] This derivative gives you the sensitivity of the output voltage to changes in the load resistance, which is directly related to load regulation. Summary

Line Regulation: Analyze the sensitivity of ( v_o ) to ( v_i ) using the derivative ( \frac{\partial v_o}{\partial v_i} ). Load Regulation: Analyze the sensitivity of ( v_o ) to ( R_L ) using the derivative ( \frac{\partial v_o}{\partial R_L} ).

• I think AI sourced answers are frowned on here, at least so far. A small-signal based analysis for line regulation will work for small variations in line voltage, but typically in power supplies the line range is more of a large-signal change. The line changes can change the FET operating point significantly, making the small-signal expression inaccurate. Commented Aug 11 at 18:08