How many address lines and how many data lines are required for a 128KB memory with 16-bit word when the memory is:

• Byte addressable

• Word addressable

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    \$\begingroup\$ Homework question? \$\endgroup\$ – Rev1.0 Jun 10 '13 at 6:52
  • 1
    \$\begingroup\$ What is your analysis so far? What do you think the answer is? We'll help you figure it out, but we're not going to just give you the answer. \$\endgroup\$ – Connor Wolf Jun 10 '13 at 6:55

There are a number of approaches to handling memory which is supposed to allow for either byte or word access. If memory were only word addressable, there would be 65,536 words of 16-bits of memory; that sets a "baseline" for the number of address and data wires required. If memory is writable on an individual-byte basis, then there are five possible types of write cycles, of which the hardware must support at least three;

    1. Write D0-D15 to a 16-bit word
  • 2a. Write D0-D7 to the lower-address byte within a word
  • 2b. Write D8-D15 to the lower-address byte within a word
  • 3a. Write D0-D7 to the upper-address byte within a word
  • 3b. Write D8-D15 to the upper-address byte within a word

In many cases, it will be easiest for the processor to support the combination (1,2a,3b) if it's little-endian or or (1,2b,3a) if it's big-endian, but interfacing an 8-bit device it may be more convenient if the processor can support either (1,2a,3a) or (1,2b,3b) [the 8-bit device would then be connected to either D0-D7 or D8-D15].

The processor will need to have enough control and addressing wires to select among all the different possible operations it will perform. This could be as few as two, but in many cases would be more. The exact number would depend upon system requirements.


The answer is 17 address lines and 8 data lines for byte addressing,


16 address lines and 16 data lines for word addressing.

You can use this to check your answers. Nice name btw.


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