I am making a CPU from discrete transistors using nmos logic. As a first step I would like to build a binary counter.
The following design seems to be optimal in terms of logic gates but my question is: are there any transistor-level (rather than logic gate-level) optimizations that could be made?
A N-input NOR gate requires N transistors so the current design uses 13 transistors.
Good question. I'll offer you a better question in return: you have to build that thing, right? So, is "least number of FETs" really the objective function here?
I'd argue it's not. When you buy MOS transistors, you'd typically buy them as pairs; and while you're at it, use some that have a built-in gate resistor, that saves a lot of work. And that makes certain gates easy, because they can be build just by wiring up a single "dual-channel" transistor package in the right way.
Say you're using the SSM6N7002KFU,LF:
Building logic gates becomes very simple: you connect pin 6 and pin 4, use 2 and 5 as inputs, and get a NAND; same for some other gates. Suddenly you don't have complex wiring connecting individual transistors, but the unit of construction becomes the "two-transistor block". That is absolutely something you'd probably come up if you had "simple" transistors, too! You basically always connect them in pairs (aside from the inverter, there's no functionality that you can implement in a single transistor, anyways).
So, how does one find an optimal implementation for some complex functionality? Well, you apply 70 years of design theory. Just kidding, you describe the components you have in a language that your circuit synthesis tool understands. For example, you'd go ahead and describe the NAND circuit as 1 "cell" (because you know how to make one out of your dual-n-Channel-MOSFET-package) with area 1, you'd describe a RS-flipflop as 1 cell with area 2 (because you know how to make one using two MOSFETs + a dual diode package), you'd describe a dual-inverter as a cell with area one, and you also describe a single inverter as a cell with area one (you just don't connect one transistor in these).
yosys allows you to define your own "technology" stack as library of such components (actually, that's by no means yosys' invention). There's people that built 7400 gate libraries, and I'm sure I saw someone implement a yosys-to-minecraft-lava-block-logic library. You can implement a small nMOS logic library, and let the synthesizer find you a (near-, in some cases, in most cases just plain) optimal implementation of a counter.
Note that I can't congratulate you to your choice of using nMOS-logic: a) that has a static power consumption, b) that's in need of level shifting practically after every 2-input gate, and c) it's less robust and harder to get right than CMOS logic. There's good reason why computers really exploded after CMOS became the cheaper-per-gate technology (see, for example, the 6502 Bugs like the nMOS-6502 "involuntary" opcodes that were fixed by using CMOS).
Yes. You can [ab]use the dynamics of specific circuits to reduce it quite far:
simulate this circuit – Schematic created using CircuitLab
This is a fairly "ancient" technique -- you find it in books on analog/sequential circuits, logic, computers, going back to the vacuum tube days (of course then using triodes and crystal diodes). Classic handbooks from the 40s to 70s will prove illuminating here (literally so, in the earlier cases when neon bulb logic was often included..!).
By chaining these stages (give or take buffering or a pulse conditioning circuit inbetween), binary cascades can easily be made.
On a related note, the 2N3904 model in CircuitLab seems busted in some way I can't easily determine. It did not work in this circuit, after trying for several 10s of minutes.
