# Ripple counter from as few transistors as possible

I am making a CPU from discrete transistors using nmos logic. As a first step I would like to build a binary counter.

The following design seems to be optimal in terms of logic gates but my question is: are there any transistor-level (rather than logic gate-level) optimizations that could be made?

A N-input NOR gate requires N transistors so the current design uses 13 transistors.

• You can probably do some diode-ors somewhere in there and swap some transistors for diodes. Commented Aug 13 at 19:19
• I considered using diodes but I think i’d rather use transistors because the cost is approximately the same and transistors seem to be more stable (less voltage drop) Commented Aug 13 at 19:31
• Your question is asking about reducing the number of transistors, not semiconductors in general, though. (and if you wanted to reduce the semiconductor count as low as possible, you could just do it all in vacuum tubes, or relays, or mag amps, or hydraulics, or mechanical linkages, or....) Commented Aug 13 at 19:33

Good question. I'll offer you a better question in return: you have to build that thing, right? So, is "least number of FETs" really the objective function here?

I'd argue it's not. When you buy MOS transistors, you'd typically buy them as pairs; and while you're at it, use some that have a built-in gate resistor, that saves a lot of work. And that makes certain gates easy, because they can be build just by wiring up a single "dual-channel" transistor package in the right way.

Say you're using the SSM6N7002KFU,LF:

Building logic gates becomes very simple: you connect pin 6 and pin 4, use 2 and 5 as inputs, and get a NAND; same for some other gates. Suddenly you don't have complex wiring connecting individual transistors, but the unit of construction becomes the "two-transistor block". That is absolutely something you'd probably come up if you had "simple" transistors, too! You basically always connect them in pairs (aside from the inverter, there's no functionality that you can implement in a single transistor, anyways).

So, how does one find an optimal implementation for some complex functionality? Well, you apply 70 years of design theory. Just kidding, you describe the components you have in a language that your circuit synthesis tool understands. For example, you'd go ahead and describe the NAND circuit as 1 "cell" (because you know how to make one out of your dual-n-Channel-MOSFET-package) with area 1, you'd describe a RS-flipflop as 1 cell with area 2 (because you know how to make one using two MOSFETs + a dual diode package), you'd describe a dual-inverter as a cell with area one, and you also describe a single inverter as a cell with area one (you just don't connect one transistor in these).

yosys allows you to define your own "technology" stack as library of such components (actually, that's by no means yosys' invention). There's people that built 7400 gate libraries, and I'm sure I saw someone implement a yosys-to-minecraft-lava-block-logic library. You can implement a small nMOS logic library, and let the synthesizer find you a (near-, in some cases, in most cases just plain) optimal implementation of a counter.

Note that I can't congratulate you to your choice of using nMOS-logic: a) that has a static power consumption, b) that's in need of level shifting practically after every 2-input gate, and c) it's less robust and harder to get right than CMOS logic. There's good reason why computers really exploded after CMOS became the cheaper-per-gate technology (see, for example, the 6502 Bugs like the nMOS-6502 "involuntary" opcodes that were fixed by using CMOS).

• You will need to talk about what your goal is, then. Because: wiring up something from an infinite supply of 2N7000s with board material, load resistors, solder that you still need to pay for is probably still more expensive than ignoring your infinite supply of 2N7000 and not doing anything. Say, a conservative estimate for the smallest CPU that you can build and that still "does" something is maybe 400 logic gates? assuming these all were NAND on average, i.e., 2 nMOS per gate, you need 800 transistors. Not counting memory! and at least 400 pull up resistors. And around 1200 connections. Commented Aug 13 at 20:49
• a single 2N7000 in its humongous TO-92 package needs some π·(5.2mm / 2)², roughly 25 mm², so, 800 will need 20,000 mm²; the densest construction made from discrete TO-92 components I've seen was probably a car radio I dissected as a kid, and if I'd take a guess, it was using about one third of the area for transistors, you won't be that dense, because you have more complex interconnect, you're not building a simple audio device. so, 80,000 mm² if you really want to hate yourself for placing things so tightly while assembling your computer. That's some 28 cm × 28 cm board. Pretty large! ANd Commented Aug 13 at 20:56
• still contains neither in- nor output, nor any memory. Is this really the rabbit hole you want to start to go down there? I mean, it certainly sounds like a cool project, and if you design PCBs that you can test individually, and for which you introduce kind of a "standard" connector so that you can build your overall system modularly, so you can build one component board while you wait for the PCB for a fixed version of another module to arrive, definitely doable. But it takes a lot of organization and planning to not go insane. Tip: distribute a higher voltage than your intended logic level Commented Aug 13 at 21:00
• to all modules, and have a voltage regulator on each one, so that you don't get into troubles trying to transport a couple ampere at 5V and then wonder why at the far end of the system, significantly less arrives :) Commented Aug 13 at 21:05
• ufff! Breadboard's going to be quite a price- and a pain point! (Assuming you mean the solderless, plug-leads-in kind) Commented Aug 13 at 21:54

Yes. You can [ab]use the dynamics of specific circuits to reduce it quite far:

simulate this circuit – Schematic created using CircuitLab

This is a fairly "ancient" technique -- you find it in books on analog/sequential circuits, logic, computers, going back to the vacuum tube days (of course then using triodes and crystal diodes). Classic handbooks from the 40s to 70s will prove illuminating here (literally so, in the earlier cases when neon bulb logic was often included..!).

By chaining these stages (give or take buffering or a pulse conditioning circuit inbetween), binary cascades can easily be made.

On a related note, the 2N3904 model in CircuitLab seems busted in some way I can't easily determine. It did not work in this circuit, after trying for several 10s of minutes.

• Neat! I didn't realize you could be that sneaky about delays :) Re 2N3904: isn't that a BJT? I think OP is going for nMOS. Commented Aug 13 at 19:23
• And vacuum tubes are metal-vacuum-semiconductors :) BJTs are probably the easier to illustrate, but the technique works generally. It's a bit finicky anyway, you'll have to play around and see. Commented Aug 13 at 19:24
• Yeah, worst case you just add a diode and a reistor gate-drain to emulate the current into the base of a BJT. But "finicky" is the word I was looking for when I saw "nMOS", anways; single-ended logic always needs these loads of "let's restore the voltage to its nominal value" intermediate stages. Commented Aug 13 at 19:27
• Yep, plus IC NMOS you can do transmission gates (moderately well), and weird dynamic gate shenanigans if you want to get really deep into the weeds; which is harder to do with BJTs, but also can't be done with discrete NMOS because the substrate is never* pinned separately. I would just as well encourage BJTs for discrete synthesis, keeping to static logic, and leveraging the decade or two of DTL and RTL design that's fairly well documented and accessible. It's practically NMOS that way, but it runs faster for less dissipation. Commented Aug 13 at 19:32
• Jfets could be used as constant current sources, can similar be done with the likes of a 2N7002 or BSS134? A ‘depletion load’? Commented Aug 14 at 6:48