In follow-up to my previous question: Resistor values in transistor logic gates

I've breadboarded all common types of transistor logic gates:
The two yellow wires are input A and B. The white wire is the inverter input.

Input A=0 + B=0 + inv=0 gives: 00

Input A=0 + B=1 + inv=0 gives: 01

Input A=1 + B=0 + inv=0 gives: 10

Input A=1 + B=1 + inv=1 gives: 11

All logic works perfect, but the voltage-drop differs significantly between the gates. For example, the XOR gate is created from AND, NAND and OR gates and each transistor increases the voltage-drop. The LED barely lights up!


My goal is to build a 4-bit calculator from transistors (using CMOS chips I did not encounter this problem). But if each logic gate results into significant voltage-drops like these, how can I ever combine 10 logic gates behind each other? I've played around with many resistor values, but most combinations render the logic gates useless. How to adjust the XOR gate above to match the voltage drop in, for example, this simple AND gate?


EDIT (response to answer by JIm Dearden)

I learned a great deal and can't stress enough how much I appreciate your answer!!!
The drawings are really clear, I'm sure many people will benefit from them in the future!

Though really obvious, I never realized:
- NOR = NOT (with two inputs)
- OR = NOR + NOT

The "base everything on a simple inverter circuit" does indeed the trick!
All logic gates, including the combined gates like XOR, output the same :)



Best wishes!

  • \$\begingroup\$ That top gate in the schematic looks wrong... \$\endgroup\$ Commented Jun 10, 2013 at 23:37
  • \$\begingroup\$ Oops! Now fixed :) \$\endgroup\$
    – Anne
    Commented Jun 10, 2013 at 23:56
  • \$\begingroup\$ @Anne This is a great project for learning about logic and computing, Its been a real pleasure to pass on my knowledge. I look forward to your next question :) \$\endgroup\$ Commented Jun 12, 2013 at 6:58

2 Answers 2


I actually did this at school back in the 60's (yes I am that old). We used them to build a small and simple 'computer' capable of addition, subtraction, multiplication and division.

The problem you have is that the gate circuit's inputs and output voltages you are using aren't really compatible. You would find it difficult to expand the number of inputs on a gate beyond two and its quite likely that the 'high' output of one gate isn't quite 'high' enough for the input of another.

What we did back then was to base everything on a simple inverter circuit (or 1 input NOR gate) and build from that.

The advantage of this approach is that you can increase the number of inputs to the gate by adding another resistor. Any input over 0.6V will operate the gate. I've shown resistor values of 10K and 4k7 (to match your circuit) but unlike your previous circuits the values here can be altered quite considerably. e.g input 470K, output 47k and it still works fine.

I've drawn out some of the basic gates - NOT, NOR, AND, NOR, NAND. Following what I have drawn I'm certain that you can produce any other gate you require.

enter image description here

You might also find these circuits useful enter image description here

And a divide by 2 (counter) enter image description here

  • \$\begingroup\$ Please see my response at the bottom of the question! One little question regarding the transistor astable multivibrator: What capacitance should be used for the capacitor? \$\endgroup\$
    – Anne
    Commented Jun 11, 2013 at 22:54
  • \$\begingroup\$ @Anne Basically the period is controlled by the value of the base resistor (10K in the diagram - but it could be more or less) and the capacitor value. The value of time on or time off is about 0.7CR. So the period will be 1.4CR. By altering the values on each side (and making them different) you can produce different mark/space ratios. For C = 0.1uF and R = 10k (on both transistors) F is about 714 Hz. 0.01uF will give about 7kHz, 10uF about 7 Hz. The values aren't particularly critical. \$\endgroup\$ Commented Jun 12, 2013 at 6:52
  • \$\begingroup\$ @DiegoCNascimento A buffer doesn't change the logic so you would need two NOT gates \$\endgroup\$ Commented Sep 9, 2016 at 8:38
  • \$\begingroup\$ I think the NAND and AND gates are labeled backwards. \$\endgroup\$
    – Stuart
    Commented Mar 17, 2020 at 17:00

You are using NPN transistors to pull the gate output up to 6V, but NPN transistors aren't very good at pulling a node high. The emitter of the NPN won't go higher than about 0.6V below the voltage at the base. If you want to use NPN transistors then only connect them between the gate output and ground with a pullup resistor to 6V. This will allow you to make NAND, NOR, and INV gates and you can make whatever kind of logic you want with those.

  • \$\begingroup\$ Thanks for your answer! To be honest, the "pullup resistor" concept is completely new to me. I'm certainly going to dig into that subject! \$\endgroup\$
    – Anne
    Commented Jun 11, 2013 at 22:46

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