# Why does this high pass filter/rc differentiator behave like this?

Take a look at this circuit below:

If I'm correct, the circuit above is an RC differentiator/high pass filter. However, I do not understand its behavior.

The circuit produces an output like so: (assuming CLK is a square wave)

However, I don't see how this happens?

For instance, here is what I think would happen

1. CLK starts low, capacitor has no charge, no current goes through resistor and out is 0v
2. CLK goes high, charges capacitor, but out is still 0v and no current still goes through the resistor. The capacitor then blocks current from CLK since it is fully charged and there exists no potential difference.

Of course, I'm wrong because the behavior in the simulator does not match what I think should happen. But I still have no idea how the circuit's behavior is found out.

So why does this circuit behave like this? Thanks.

• The voltage across a capacitor can't change instantly, right? It integrates the current through it. So what happens to the voltage across the resistor when CLK goes high? Commented Aug 24 at 23:58
• You are running the circuit in a simulator. What prevents you from finding out why the circuit behaves like it does, square wave charging and discharging the capacitor with current? Commented Aug 25 at 0:44
• With respect to the steady state behavior (after the transition from initial conditions), there are three distinctive areas of interest: (1) $\frac1f\lt \frac{R\cdot C}{10}$; and, (2) $\frac1f\gt 10\cdot R\cdot C$; and, (3) $\frac{R\cdot C}{10}\lt\frac1f\lt 10\cdot R\cdot C$. You should probably explore all three. Don't just look at the output itself, but also examine a separate trace of the voltage across the capacitor, as well. Commented Aug 25 at 1:44

If I'm correct, the circuit above is an RC differentiator/high pass filter

It is a high-pass filter. It's not an ideal differentiator.

CLK goes high, charges capacitor,

Yes, but it charges the capacitor eventually.

but out is still 0v and no current still goes through the resistor. The capacitor then blocks current from CLK since it is fully charged and there exists no potential difference.

This is approximately correct, asymptotically, after charging is complete. This corresponds to the flat part of the output curve after each spike dies down.

However, all of this presumes that the capacitor was charged to reach the necessary charge across it to make Vout = 0. In order to actually charge it, a current must flow, as predicted by the branch constituent equation $$\I = C \frac{dV}{dt}\$$. Each time the input voltage changes, the capacitor charges and the charging current dies down exponentially.

By KCL at the output node, that current must go through the resistor (there is nowhere else for it to go), and that leads to a proportional voltage due to Ohm's law across the resistor.

• Hi. Thanks for your response, appreciate it. However, I have one more question. When CLK goes low, cap should discharge right? dv will be negative therefore current is negative/opposite direction and CLK sinks the current? But how can the vout be negative? Vout = Vr since they are parallel but Vout being negative implies that GND is higher potential than the other side of the resistor and charge flows from GND? How can that be the case? Thanks. Commented Aug 25 at 0:22
• No the resistor drains the cap to gnd. So a negative edge tries to go to -(Vdd) which exceeds "Not to exceed" levels for CMOS then returns to gnd. Commented Aug 25 at 0:45
• @Mahad The cap discharges, causing a current to flow in the opposite direction, which (by Ohm's law) gives you the negative spike. I'm not sure why D.A.S. mentioned CMOS here since there doesn't seem to be any MOS gates involved in the circuit. Commented Aug 25 at 1:20
• @Mahad when the clk is steady high and circuit output is zero, the left side of the cap is positive with respect to right side and no current is flowing in R or C. When the input clk switches to low (0 V) then the voltage across the cap CAN NOT change until the charge flows, which must take time because limited by R and not instant. As the left side of the cap is forced to new voltage with respect to gnd by Vclk driver switching to gnd, yet the left side of the cap to MUST remain higher voltage than the right side, so the right side becomes negative with respect to ground. Commented Aug 26 at 4:39