Why is my "common gate amplifier" introducing a zero when it shouldn't be introducing one as per theory?

Question

I am trying to simulate a cascode circuit followed by a source follower in LTSpice and observe its frequency response. I added a 100GH inductor to serve as negative feedback only for DC, i.e., the circuit functions as an open loop in the AC simulations. This is the schematic of the circuit:

^{simulate this circuit – Schematic created using CircuitLab}

V_X is at 964 mV (DC), and V_Y is at 1.15 V (DC).

I have turned off the body effect (shorted the source and bulk for all the MOSFETs) to simplify my analysis and have verified that all the MOSFETs are in saturated inversion.

As per my theoretical understanding, the circuit should have only two (high frequency) zeros, one from the common source MOSFET M1 and one from the common drain MOSFET M5, but the AC response shows that it has three zeros— one each from CS M1, CG M2 (~ 1.5 GHz, very obvious in the v_y/v_x bode plot), and CD M5.

When I remove the L₁ from the circuit, M2 no longer introduces the zero, but it reappears when the loop closes again.

I have tried to debug the CGA by itself to figure out the source of the problem and am using the following circuit for it:

^{simulate this circuit}

So far, I have noticed that this circuit also presents the same zero (at the same frequency), and the zero disappears when I replace the MOSFET with a BJT. I have also turned off all capacitances (C_DB, C_SB, C_GBO, C_J, and C_JSW) apart from C_GS and C_GD in the Level 1 SPICE MOSFET Model I'm using.

I have also noticed that this zero disappears as soon as my V_Y increases beyond 1.6 V. But this is a DC voltage, and it should not impact the AC frequency response in any way as long as the MOSFET remains in saturated inversion. So, observing this does not make much sense to me.

I think (maybe wrongly) that the C_Oxide component in the C_GS capacitance is somehow introducing this zero, but I'm not sure. Does anyone know why the zero could appear in the circuit and how I could resolve the problem?

Any input is highly appreciated.

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Edit 1: I simulated the circuit in both Cadence and NGSpice. The CGA zero was absent from there. This leads me to think that LTSpice is doing something ridiculous and inserting a zero where it shouldn't be. Does anyone know why or how LTSpice is doing this?

Edit 2: Added simulation details to the debugging circuitry.

Answer 1

I'll first clarify the problem you're having, since your question doesn't highlight it very well and it took me a bunch of screwing around to get my footing. You're getting the following in LTspice, where there is a zero in the frequency response at around ~1.5GHz. This is where slope of the phase changes directions and the magnitude response begins to flatten out.

If you compare this to other SPICE programs, the zero does not exist and the magnitude response keeps rolling off. Below is what the same netlist generates in ngspice.

Another difference between the two is that the LTspice magnitude response begins rolling off much earlier (at ~100KHz) compared to ngspice (at ~10MHz).

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I believe you're on the right track when you say this:

I think (maybe wrongly) that the COxide component in the CGS capacitance is somehow introducing this zero, but I'm not sure.

If you look at the SPICE Error Log in LTspice CTRL+L when you run the simulation, you get a warning that says the gate oxide thickness Tox is too thin. I believe the warning is to tell you that with such a thin oxide defined you can get unwanted effects with this model...and that is what seems to be happening.

According to the LTspice built-in help for M. MOSFET, it mentions that LTspice implements something differently when Tox is defined.

Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the non-linear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Channel capacitance is implemented as a Yang-Chatterjee charge-based model in all aspects of simulation but legacy Meyer capacitances are reported in the SPICE log file. The thin-oxide charge-storage effects are treated slightly different for the Level=1 model. These voltage dependent capacitances are included only if Tox is specified.

Learning from this, if you remove the Tox parameter from the .model definition the plot now matches what ngspice produces.

Alternatively, you can increase the Tox value and the zero will be pushed farther out. The following is when tox=50n.

So I believe you're right that the zero is coming from here. Unfortunately, I do not know the underlying equations that LTspice uses to calculate the extra Tox capacitance. More generally, for higher frequency amplifier applications the lower level MOSFET models (1, 2, and 3) should be avoided when possible. If you're using a thin Tox, you might want to look into using one of the BSIM models instead.