Splicing buses in KiCad

Question

I would like to be able to splice two buses in KiCad into a third, larger bus.

Say I have a subsheet with an output pin connected to a 16-wire bus (an unrelated note: it took me a while to figure out how to get buses through a subsheet but it works). I have another sheet where I place several identical copies of that subsheet and I want the output of that sheet to be an N*16 bit bus to be used in the top-level sheet. As an illustration, here is a simplified example of what I want to achieve:

The first bus passes through perfectly, (e.g. lines 1-16 have associated nets and are properly placed in pcbnew), however the second bus (lines 17-32) doesn't get connected

I figured out a way around this by assigning each subcomponent bus a separate unique bus name and then mapping each one, pin by pin, to the corresponding pin on the master bus. It is, however, rather inconvenient given that the full schematic has 512 total lines in the bus ( :O ).

The not-so-convenient-solution is illustrated below (not all pin assignments are shown for clarity).

In short, the question is if there is a way to get around bit-banging all the buses together like this and have a solution more like the first non-working method.

PS. Before anyone asks, this doesn't work either:

Answer 1

For splicing buses the key point to remember is that the name is ignored and the connection is carried out solely on the basis of the line ID. To illustrate this I have spliced 3 buses in the example below: ETH_RGMII, USB_ULPI, and UART into a single bus COMM by connecting labels as follows.

ETH_RGMII[0..14] → COMM[0..14]

USB_ULPI[15..27] → COMM[15..27]

UART[28..31] → COMM[28..31]

As a result of this restriction if one were to change the indices on UART to [0..3] then no connections would be made due to the lack of matching indices on the "UART[0..3] → COMM[28..31]" connection.

One can take advantage of this to make splicing more flexible by incrementing the starting indices of the individual buses to be spliced by 100 (spaced indexing) so that one can flexibly resize the individual channels without having to worry about unintended connections.

In this scenario the 3 channels are now connected with as follows:

ETH_RGMII[0..14] → COMM[0..99]

USB_ULPI[100..112] → COMM[100..199]

UART[200..203] → COMM[200..299]

If I were now to expand the USB_ULPI bus by a few lines this eliminate the need to re-index UART.

Answer 2

The EESchema reference manual section "Global connections between buses" explains this. Bus wires with a junction.

Answer 3

This does not work for KiCad 6.0. After failing to replicate this in kicad 6.0, I found this relevant section of the EESchema manual.

Buses with more than one label KiCad 5.0 and earlier allowed the connection of bus wires with different labels together, and would join the members of these buses during netlisting. This behavior has been removed in KiCad 6.0 because it is incompatible with group buses, and also leads to confusing netlists because the name that a given signal will receive is not easily predicted.

Source: https://docs.kicad.org/6.0/en/eeschema/eeschema.html, 2022-08-23.