# Voltage regulator device selection

I intend to design a CMOS voltage regulator that takes 2.5V supply and outputs 1.2V. I am starting off with an opamp+pass transistor design.

Will there be a specific advantage to using an NMOS pullup device vs PMOS pulldown for the pass transistor?

Additional details: The regulator supplies this constant voltage but is also supposed to sink a lot of current (~5 mA)

• This is an IC design or a discrete components design? – The Photon Jun 13 '13 at 23:19
• Sorry. It is an IC design question. – BobLobLaw Jun 13 '13 at 23:21

The primary advantage of an NMOS transistor is that the higher mobility of electrons means that you can use a physically smaller transistor to pass a given amount of current. Of course, the disadvantage is that if you use an NMOS pass transistor then the maximum $V_{GS}$ you can provide is 1.3V, but if you use a PMOS transistor the maximum $V_{GS}$ is 2.5V. Since you want to sink as well as source current the typical way of doing this is to add a fully complementary buffer (i.e. a big inverter) at the output of the op amp, with a PMOS to 2.5V and an NMOS to ground.