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Could someone explain the voltage translation "Magic" that is happening in the circuit in the link below?

Voltage Translation Magic!

The YRPBRL78G13( blue on the left ) is a 5V design and the cc3000 module is a 3.3V design.

I can't understand how the arrangement of LDO and pullup (pulldown?) resistors would achieve voltage translation.

I've tried simulating this, and as far as I can tell this shouldn't work.

All help is appreciated!

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  • \$\begingroup\$ Looking at page 84 of the documentation it looks like the pins have be set to TTL or open drain "Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg)." \$\endgroup\$ – JIm Dearden Jun 14 '13 at 10:08
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Another possibility could be that the pins on J1 that interface with J4 are not really 'outputs'. If its in a tristate/input or if its driven low (yes this is an output), then J4 never sees anything to do with 5V. Its all done via the the 10k pull up and J1 since little current through its pins.

Because J1 is a 5V device, as Ignacio Vazquez-Abrams pointed out, the threshold for a HIGH would be about 2.2V which and since the J5 would ouput 3.3V, its enough.

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  • \$\begingroup\$ I've looked at the output topology for the pins in question, they are CMOS outputs. while it would be possible to set the output low and then toggle the pin mode from input to output to achieve the effect you describe, the source code accompanying this circuit uses the hardware SPI peripheral, which does not do this. \$\endgroup\$ – MrRadiotron Jun 14 '13 at 6:13
  • \$\begingroup\$ My apologies, the ports in question can be configured to be Open Drain outputs. This was not obvious from the I/O circuit diagrams, and only apparent from the Port Function block diagram. \$\endgroup\$ – MrRadiotron Jun 14 '13 at 6:42
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The RL78/G13 has some TTL-compatible inputs, which have a VIH of 2V2. This is easily reachable by 3V3 CMOS logic.

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  • \$\begingroup\$ beat me too it :( \$\endgroup\$ – efox29 Jun 14 '13 at 4:28
  • \$\begingroup\$ This explains only one aspect, the 3v3 to 5v direction. \$\endgroup\$ – MrRadiotron Jun 14 '13 at 6:08

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