Multi-Layer PCB Stack-Up Order and LVDS Signal Routing

Question

I'm working on a multi-layer PCB design that includes Top and Bottom layers, as well as internal layers for GND, VCCs, and signal routing. I'm uncertain about the proper stack-up order for these layers. What would be the best way to arrange them between the Top and Bottom layers? Additionally, is it acceptable to route signals on internal layers, or should signal routing be limited to the outer layers only?

Unfortunately, I wasn't able to route my LVDS signals on a single layer, so I will have to route them across more than one layer. Any advice on how to handle this situation? This is my first suggestion:

1. Top Layer (TOP) – Components and signals.
2. Internal Layer 1 (GND) – Continuous GND plane.
3. Internal Layer 2 (VCC 4.3 V) – Power plane for 4.3 V.
4. Internal Layer 3 (VCC 1.8 V) – Power plane for 1.8 V.
5. Internal Layer 4 (Signal) – Dedicated signal layer for routing LVDS signals adjacent to the GND plane.
6. Bottom Layer (BOTTOM) – Another signal layer or additional components.

What do you think about it ?

Answer 1

Unbalanced layers isn't a good idea. You want similar copper density to reduce board warpage.

That is, what you do (in terms of purpose and density) on the top 3 should be mirrored on the bottom 3, etc.

Two 6-layer stackups are typical:

1. Sig-GND-sig-sig-VCC-sig: tons of room for routing, stripline available (mid layers)
2. Sig-sig-GND-VCC-sig-sig: tons of routing again; outer pairs may not be controlled impedance (or as easily), or, more crosstalk for adjacent or crossing traces (between layers), but more proximity to the surface can have useful implications (signals traveling close under a SMT device, short depth distance required, no crossing planes). The planes may be very close together (layer pairs stackup) for especially low impedance.

If you don't need the mid layers for signals, or need a lot of power (high current or low impedance), they can just as well be pours, in which case sig-GND-VCC1-VCC2-GND-sig might be used. Unused areas can be filled with GND to maintain copper density.

Whatever the environment, choose suitable layer thicknesses and trace widths to get the required differential impedance (and CM if specified). Since between-planes traces are surrounded by dielectric (stripline), they have lower velocity and impedance (per width) than microstrip, and different preferred widths apply for a given transmission line impedance.

Answer 2

What do you think about it ? I would not run the LVDS signals under a layer with other traces on it. Think about it, there is capacitance between layers (without a reference plane on both sides) with no layer in between 4 and BOT, you run the risk of crosstalk. It also doesn't make sense to have a dedicated layer just for one VCC (most of the time).

Internal Layer 4 (Signal) – Dedicated signal layer for routing LVDS signals adjacent to the GND plane Bottom Layer (BOTTOM) – Another signal layer or additional components

What to do?

use this: Internal Layer 4: GND Bottom: LVDS

Make sure you if you are running diff pairs, you have 3x diff pair width clearance on either side where possible. And 2x for Single ended transmission lines.

You can also run LVDS on inner layers, between two grounds or between a VCC and GND plane (Edge coupled internal asymmetric diff pairs) but if you have breaks in either GND or VCC plane, you need decoupling capacitors to bridge the gap.

Answer 3

I would go with something like this:

SIG/PWR GND SIG/PWR GND SIG/PWR GND

If you plan to route the LVDS on more than one layer, you have to consider the reference plane. If you change layer, what is then the reference plane for the signal and how does the current come back to the source?

In general have a GND plane next to each signal or power plane.