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What's so special about NAND & NOR(apart from being universal gates) that most books on digital design try to emphasize design using these gates?

Is it easy to manufacture or something?

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NAND and NOR are preferred because they are smaller and use less power in a CMOS process than equivalent AND or OR gates. NAND and NOR gates can be created with 4 transistors, while AND/OR require 6.

An AND/OR gate is laid out in a cell library generally as a NAND/NOR followed by an inverter.

enter image description here

AND Gate (OR is similar)

enter image description here

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    \$\begingroup\$ I'd just like to point out that less transistors and less stages means less propagation delay, too, and that is very important as you move on towards high-speed devices. \$\endgroup\$ – fuzzyhair2 Jun 15 '13 at 3:50
  • \$\begingroup\$ I think it's worthwhile to note that there's no requirement that an inverting gate either consist entirely of "and"ed terms or "or"ed terms. If it's necessary to compute "not (A and B) or (C and D)", one would likely use eight transistors to compute it directly, as opposed to computing "not ((a nand b) nand (c nand d))", which would require 14 transistors (four each for the initial "nand" terms, four to "nand" those together, and two to invert the result. \$\endgroup\$ – supercat Jun 15 '13 at 19:29
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NAND and NOR gates are arguably more flexible than AND and OR gates because you can also turn them into inverters. Once you have inverters, you can basically create any gate you want. Below is a cool chart that shows how to turn a NAND gate into the other kinds of gates.

enter image description here

What @Tim said about the physical size of NAND and NOR gates is absolutely true, but I'd also like to point out that this doesn't matter when talking about Quad-Gate chips like the more modern versions of the 74xxx type chips. The reason why that is is that the I/O Buffers and pads on the chip itself are much larger than the actual gate, so the difference between 4 transistors and 6 doesn't really change the price much (if at all). It does matter for larger chips where you have millions of gates and the size of the logic is much larger than the size of the I/O.

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An historical perspective.

In the early days of logic circuits the easiest gates to build were NOR gates (you could even build them with thermionic valves/tubes). Much of the inital work (and maths) was done in NOR gate building blocks. enter image description here

With the advent of integrated circuits and especially the 7400 logic series came the multiple emitter transistor and so the focus changed to NAND gates as the basic building block.

enter image description here

Then came CMOS (4000 series gates) that could create both types of gate without the penalty of extra devices. (It also decreased power consumption, size of chip, increased voltage supply range etc. etc.)

The rest, they say, is history.

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  • \$\begingroup\$ I find the TTL design somewhat curious. By my understanding, the design of TTL chips essentially replicates the design of discrete-transistor TTL electronics, but such circuitry would seem rather bulky. I could understand putting a nice driver on a gate which has a fan-out of ten or more, but I would think that in many devices a substantial fraction of gates would have a fan-out of exactly one, and I'd guess the majority would have a fan-out no greater than two. Could/did designers optimize around that fact? \$\endgroup\$ – supercat Jun 15 '13 at 19:42
  • \$\begingroup\$ @supercat The engineers and designers at that time could only draw on what they knew - discrete transistors (based on circuits initially developed with valves). It was about the miniaturization (small scale integration) of existing circuits rather than developing new ones. This produced devices like the 555, the 709 and 741 op amps and of course the 7400 series. I doubt if big fanouts were a design priority back then. Certainly fanout was an issue for for me designing/constructing actual circuits. Then things changed dramatically in the early 70's when micros came onto the scene. \$\endgroup\$ – JIm Dearden Jun 15 '13 at 21:10
  • \$\begingroup\$ I was wondering about the extent to which such techniques were used both within chips, and also in the computers which immediately predated the era of TTL chips. It's possible to design an inverting full adder (X+Y+Z yielding Sum and Carry outputs) using two transistors and a bunch of resistors; such a circuit will be slow, but if transistors are expensive, it may be a lot cheaper than a full adder implemented in TTL logic. \$\endgroup\$ – supercat Jun 15 '13 at 21:27
  • \$\begingroup\$ @supercat Not with just two transistors. You could certainly build a full adder but it would take a lot of transistors (I know because I built one back in the 60s ). Transistors aren't that slow and could be faster than TTL chips. The cheapest and easiest solution today would be to use a small microcontroller. \$\endgroup\$ – JIm Dearden Jun 15 '13 at 21:57
  • \$\begingroup\$ Two transistors for a full adder. Both transistors have their emitters at ground, and have pull-ups on their collectors (which provide inverted sum and carry outputs). The first transistor has a pull-down on its base, and has resistors to the three inputs sizes so that it will turn on when two of the three inputs are high. The second transistor has a pull-down on its base, and resistors to the three inputs as well as the first output, sized so that it will turn on when at least one of the three inputs is high but the first output isn't, or when all three are high. \$\endgroup\$ – supercat Jun 15 '13 at 22:25

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