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Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.

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  • \$\begingroup\$ Can an open source Verilog linting tool be designed collectively or is any group working on it? \$\endgroup\$
    – Osaid
    Commented Jun 28, 2013 at 13:06

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The best tool I know for linting Verilog is Verilator. Check the --lint-only option if you don't need the simulation.

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