# Purpose of the logic gate configurations on the Kenbak-1

I was just looking through the schematics of the Kenbak-1 computer (long story), and I found this:

simulate this circuit – Schematic created using CircuitLab

I hurt my brain a little bit trying to figure out what that flip-flop does, but mostly why those two NAND gates aren't just inverters... and why the one on the bottom (and the inverter next to it) are even there.

What's the point?

(Note: I haven't had my coffee yet.)

• You should wait with accepting the answer and allow others to have a look and write up their theory. An answered question will attract less visitors. It is good practice to wait with accepting for about 24hrs, so all timezones have had a chance to take a look. Jun 15, 2013 at 18:40
• I am part of a retrocomputing association and we are studying kenbak-1, would it be possible to have a copy of the electrical diagrams? thank you! Mar 20, 2021 at 14:32

1. The Flip Flop divides the clock by two, and makes a perfect 50% duty cycle clock.
2. I think the NANDs are surplus in already available packages on the board, so why not use them if they are fit for the job? They may also function as a fan out buffer (increase output current).
3. The NOT2 inverter looks like it is an open collector (in contrast to the NAND) type with a pull up resistor.
4. Unsure why the diode is there.

Part numbers may support this theory.

• Re: #2 - that's about what I figured; I was just making sure that there wasn't some important functional difference there. (Output current is minimal.) Jun 15, 2013 at 18:36
• Re: #3 - Would it work, then, to replace the NAND and NOT there with an open-collector buffer? I'm slightly obsessive-compulsive about excess logic, in case you haven't noticed. Jun 15, 2013 at 18:37
• If changed delay isn't an issue, but it'll probably cost you an extra chip. Jun 15, 2013 at 18:39
• Heh, yeah... that diode... "just to make sure"! I removed it already in my design. Jun 15, 2013 at 18:55

Timing, that's your answer. With old digital logic you always consider the propagation delay of each gate in your designs in order to synchronize timing. Often logic elements were added to do no more than increase the propagation delay of a given signal line, not for their "logical" functionality. I've done such designs myself mostly with TTL logic, albeit many years ago.