I have an electronics design, that is sensitive to the output capacitance.
How does Co(er) (or Coss, as Co(er) must be the integration of Coss over the bias voltage right?) vary when the device ages?
Does the capacitance increases? decreases?, or mainly remains the same?
I am looking for a MOSFET datasheet that contains aging drifts.
The aging drift is insignificant (perhaps fractions of a %).
If your design is sensitive to C, you will have more issues with normal sample-sample variations (perhaps 20 % or more from one manufacturer), and general variations with temperature (the C total doesn't change much, but the C vs. V curve shifts with temperature.
In addition, your overall gain (gm, ROUT) will vary significantly (easily 50 %) with temperature -- this will dominate over C variations.
I would not expect it to change much, and I've certainly never seen it mentioned on a datasheet.
There are known effects which result from charge trapped in the gate oxide which shift the threshold upward over time. That would presumably affect the gate charge, but maybe not the output capacitance.
You can see an effect like this if you bias a CMOS op-amp with a differential voltage for a period of time (say, using it as a comparator) - the input offset voltage will tend to shift as a result. Some of the effect may dissipate over time or with thermal annealing.
Suggest looking for IEEE and other scientific papers on transistor aging. I think you're way outside of what would be on a datasheet, and probably outside of what would be covered in application notes as well.
Thermal stress:
A mechanical stress can be induced by thermal cycling. A difference in thermal expansion coefficient on neighboring layers in the assembly of the component can result in shear stress, that affect the integrity of the transistor. The paper “Towards Prognostics of Power MOSFETs: Accelerated Aging and Precursors of Failure” from NASA [2] reports an increase of Rds_on with temperature and aging, but does not report a change in capacitance.
Electrical stress:
The document “Physics-of-Failure Approach to Prognostic” from NASA [3], presents the results of an electrical stress on the transistor gate, created in high-current conditions. The failure mode is an increasing threshold voltage, until the failure becomes irreversible (see page 35). No impact on the output capacitance is identified.
According to “Transistor Aging” from the IEEE [4], this effect is explained by hot carriers injections. This mechanism charges the metal oxide layer with carriers, which increases the threshold voltage (Vth). The physical structure of the transistor is not affected, and therefore would not have a significant impact on the capacitance.
[2] “Towards Prognostics of Power MOSFETs: Accelerated Aging and Precursors of Failure” NASA. https://ntrs.nasa.gov/api/citations/20110014227/downloads/20110014227.pdf
[3] “Physics-of-Failure Approach to Prognostics” NASA. https://ntrs.nasa.gov/api/citations/20170011538/downloads/20170011538.pdf
[4] “Transistor Aging” IEEE. https://spectrum.ieee.org/transistor-aging
Lifetime drift conclusion:
The output capacitance of the solid state relays are defined by the physical dimensions of the transistors making up the component, and no aging mechanism is identified that will affect this.
There is therefore no expected impact of aging on the output capacitance or the threshold at which the impedance error will be detected.
