I am working with P89V51RD2 which is a 80C51 micro-controller. It has Eight Interrupt Sources and Four Priority Levels.

Snapshot from datasheet of p89v51rd2 uC

In the above table, there is a column Service Priority which sounds like Fixed-Priority interrupt servicing. And then there are two bits for setting priority of individual interrupts(Interrupt Priority) which makes 4 levels.

I couldn't find the explanation for Priority Bits in the datasheet. What exactly is the purpose of these priority bits?


In this MCU the interrupt priority levels allow you to assign each device interrupt source to one of four interrupt priority groups. Devices generating interrupts in a higher priority group are capable of causing an interrupt to occur even if the MCU is already processing an interrupt in a lower priority group.

The Service Priority level within a particular group is used to determine which device will get first chance to interrupt the MCU when more than one device in the same group are asserting an enabled interrupt request at the same time. Interrupts within one group are processed serially in the Service order until all interrupts in that group are completed.

When interrupt processing within a higher priority group is completed then interrupt processing within a lower priority group will be allowed to resume. If new lower priority group interrupts occur while a higher priority group is in process then those have to wait until the higher group is completed. If a lower priority group is in process and interrupts in a higher priority group occur the processing for the lower group is suspended so that the higher priority group can be processed.

Context state for any suspended interrupt is held on the stack for the program counter location similar to the way the program counter for the main line program is held when an interrupt occurs. Any common registers in use, such as A, B or DPTR, need to be also saved to the stack if they are in turn used by the higher priority interrupt service routine. The same would also be true for the R0-R7 registers if a single/shared bank mode is in use for the registers. The 8051 architecture does have four register banks and sometimes certain banks are allocated for interrupt usage at certain priority levels. This can save a lot of extra stack pushes and pops when a high priority interrupt needs to process in a very short period if time.

Highest priority interrupt levels are normally used for extremely time critical service routines where latency needs to be kept to an absolute minimum. Hand in hand with that highest priority interrupts are often those that are coded with the smallest amount of execution time - although this is not always the case.

  • \$\begingroup\$ So if I put Timer0 Overflow into the hightest of these four level priority then it should pre-emp the INT0 interrupt. Among these four priorities which is highest 0 or 3 ? \$\endgroup\$
    – vvy
    Jun 17 '13 at 8:02
  • \$\begingroup\$ @vvy - Yes, Timer0 would preempt provided you put the INT0 onto a lower priority level. If they were on the same level they would be processed in the serial priority order for the level. --- As far as which Level number if highest priority it may take an experiment to be 100% sure. NXP's data sheet is not explicit in specifying which is higher. Note from the data sheet that the level selection bits default to 00b and the diagram in Figure 27 appears to show all selection switches in the default position. That same figure shows the default as being the lowest priority level. (Continued) \$\endgroup\$ Jun 17 '13 at 10:25
  • \$\begingroup\$ (Continued from above) It makes sense that they would make this 4-level priority system have 11b be the highest priority. The old legacy standard 8051 architecture has two interrupt priority levels with the defaults being selected at 0 and with level 1 being the higher priority. \$\endgroup\$ Jun 17 '13 at 10:28
  • \$\begingroup\$ That makes sense. And Also completes the answer. Thanks ! \$\endgroup\$
    – vvy
    Jun 17 '13 at 10:47

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