2
\$\begingroup\$

Below is a VHDL code of a even/odd parity generator for a bus of given width.

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;
use ieee.math_real.all;

entity paritygen is
    generic( WIDTH : positive := 8 );                          -- Bus width
    port   ( abus  : in std_logic_vector( WIDTH-1 downto 0 ); -- n-bit Bus
             even  : out std_logic;                           -- Even parity bit
             odd   : out std_logic );                         -- Odd parity bit 
end paritygen;

architecture behavioral of paritygen is
begin    
    process( abus )
        variable sum  : unsigned( natural( ceil( log2( real( WIDTH + 1 ) ) ) ) - 1 downto 0 );
        variable remdr: unsigned( natural( ceil( log2( real( WIDTH + 1 ) ) ) ) - 1 downto 0 );
    begin
        sum   := (others => '0');
        remdr := (others => '0'); 

        for i in abus'range loop
           sum := sum + unsigned( abus(i) );
        end loop;

        remdr := sum MOD 2;

        if ( remdr = 0 ) then
            even <= '1';
        else
            even <= '0';
        end if;
        odd  <= not even;
    end process;    
end behavioral;

When I compile the code in Synopsys Synplify Pro I get an error on the following line:

sum := sum + unsigned( abus(i) );
error: @CD715: Cast of incompatible types

In this line, I am calculating a running sum (of unsigned type) of all bit-lines of the bus. As bus is of type std_logic_vector, I am casting it to unsigned type before using add operator to calculate sum.

The error vanishes if I remove the explicit casting. I am confused as to why this is incompatible casting because as I know std_logic_vector should be casted explicitly to unsigned type using unsigned keyword. Can anyone tell me what is wrong in my vhdl code ?

\$\endgroup\$
2
  • \$\begingroup\$ have you tried using ... + unsigned( abus(i downto i) ). I did not check this with my synthesis tool, but is is possible that abus(i) returns a value of type std_logic and not std_logic_vector. It is however strange that the code synthesizes fine with no type cast at all... \$\endgroup\$
    – andrsmllr
    Jun 17, 2013 at 19:10
  • \$\begingroup\$ @damage: I think I too think that the problem is with return value of abus(i) of type std_logic. I will try with the syntax you mentioned. Thanks \$\endgroup\$
    – nurabha
    Jun 17, 2013 at 21:56

2 Answers 2

1
\$\begingroup\$

Problem here is that abus(i) is of type std_logic and no vector. Inserting a '0' helps to create a vector that can be casted to unsigned:

sum := sum + unsigned( '0' & abus(i) );

Here's a helpful numeric_std cheat sheet: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

\$\endgroup\$
0
0
\$\begingroup\$

Not sure off the top of my head, but don't you need to throw to_integer() around it? E.g.,

sum := sum + to_integer(unsigned( abus(i) ));
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.