# How do we access individual signals that are grouped into a bus: input[4:0] in1; in verilog

I need to burst

input [4:0] in1;


into subparts so that i can display every bit separately.I don't know how i can do it.

the signals should be accessed like this

input in1:0
input in1:1
input in1:2
input in1:3


or in a similar manner but not be in the form of a bus.

Edited:

This is as per limitation of a synthesis tool.In that tool after synthesis in the netlist generated, is like this

module test ( in1, in2, out);
input [3:0] in1;
input [3:0] in2;

output [4:0] out;


so i want yo ask that what is the alternate way of writing

input [3:0] in1;
input [3:0] in2;

output [4:0] out;


ofcourse not in bus([4:0]) form but bursted or in blast form.

• What do you mean by 'display every bit separately'? It sounds like you are trying to work around a limitation in your simulator; is that right? – Justin Jun 18 '13 at 12:25
• no, i am just trying to remove the limitation.Actually in every module in my tool, we use to have bus, like i explained in my question.So instead of writing input [4:0] in; , i want to write every bit seprately means for first input bit of in1, second bit of in1, 3rd bit of in1, 4th bit of in1. – shailendra Jun 18 '13 at 14:37

If you mean accessing an element in the array, then it should be more like this

For structural modeling

module input_set
( input wire [4:0] in,
output wire out
);

out = in[0]

endmodule


or

module input_set
( input wire in0, in1, in2, in3,
output wire out
);

output = in0

endmodule


In behvioral modeling it is common to use always, but the main difference is the continuous assignments.

module input_set
( input reg [4:0] in,
output reg out
);

always @ (in[0], in[1], in[2], in[3])
assign output = in[0]

endmodule


Background Knowledge:

In general there are two main groups of data types: Net and Variable. I just showed you how to use one type of Net data (wire). The variable types are reg, Integer, Real, Time, and Realtime

We use continuous assignments for Net data types and procedural assignments for Variable data types.

You should read about the different types of modeling: Structural, Behavioral and User-Defined Primitives (UDP) I'd recommend reading some books, here's a good one http://www.amazon.com/Advanced-Digital-Design-Verilog-Edition/dp/0136019285/ref=sr_1_5?ie=UTF8&qid=1371727816&sr=8-5&keywords=verilog

• i dont understand when people are replying, how others can't understand the same question......this is really bad.. – shailendra Jun 19 '13 at 14:43
• @shailendra Is this a 4x1 or a 4x4 bus? – Iancovici Jun 19 '13 at 15:25
• its 4x1 bus, i am not sure though. – shailendra Jun 19 '13 at 15:29
• @shailendra It would help if you mentioned some context, so others could understand it. Not everyone uses the same tools or languages. – Anindo Ghosh Jun 19 '13 at 16:01
• @AnindoGhosh:I am using a synthesis tool as i described above in the problem statement.All i want to do is to split pins connections from bus to separate individual pins.As i am new to verilog, there is something called blasting a bus or bursting a bus.I asked in that context , thathow we can perform the operation of blasting a bus i.e. in my case it is input [3:0] in2; in seprate individual pins. – shailendra Jun 20 '13 at 6:11

## protected by KortukJun 18 '13 at 13:31

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