I need to burst
input [4:0] in1;
into subparts so that i can display every bit separately.I don't know how i can do it.
the signals should be accessed like this
input in1:0 input in1:1 input in1:2 input in1:3
or in a similar manner but not be in the form of a bus.
This is as per limitation of a synthesis tool.In that tool after synthesis in the netlist generated, is like this
module test ( in1, in2, out); input [3:0] in1; input [3:0] in2; output [4:0] out;
so i want yo ask that what is the alternate way of writing
input [3:0] in1; input [3:0] in2; output [4:0] out;
ofcourse not in bus([4:0]) form but bursted or in blast form.