Say I want to have the 90Ω differential impedance on the USB data lines, on a triple-stacked type A USB connector, where D3 and D2 ports share the same USB data lines:
Would it make more sense to connect them like this, to lessen the reflection due to the impedance mismatch from the transmission line changing in width:
Or the signal integrity would be better if I try to keep the 90 Ohms impedance with the tracks: (But there will be more reflections due to the impedance mismatch here):
The best approach would be to use EM simulators on the design and then a TDR (time domain reflectometer) on the physical PCB, but I have none of these tools. Until now, I always go with the first approach, aka if I can not keep the impedance the same all through the transmission line, I would "submit" to the change and I would keep the "new impedance" as long as needed (even if the tracks were longer in this example), so that I have as few changes on impedance as possible.
Same question for a single transmission line, assuming I want to keep the impedance the same and I need to make the track thinner at one point. After that point, Is it better for signal integrity to increase the width of the track again (bottom picture) or keep the thinner track (top picture)?
Again, in this case I always pick to keep the thinner track, as I assume there will be less reflections overall.
- What is the approach for example on a same problem, but with faster signals, like DDR memories on motherboards design?
- Maybe this is a question with answers based on each individual cases and can only be answered using simulations and TDR to measure the impedance changes?