I can imagine scenarios in which DAC output resembles the error signal of a linear servo. If the DAC has an output from 0V to +1V, and the ADC is searching the digital space for some value corresponding to +1V, then the bit trials might take the following sequence:
100000 → 110000 → 111000 → 111100 etc, corresponding to this DAC output:
That very much looks like a critically damped servo, following an exponential approach to the set-point, with time constant \$\tau \approx 63\% \times n\$, where \$n\$ is the number of bits. I'm not sure how you would characterise gain here.
In trials to find 668mV, the sequence could be:
100000 → 110000 → 101000 → 101100 → 101010 etc.:
This resembles an under-damped system, overshooting at every trial.
I don't have anything more quantitative to offer, I'm afraid. The discrete nature of the system thwarted my efforts. My intuition tells me that such behaviour cannot be characterised by a linear transfer function, because sometimes it is critically damped, other times it isn't, but I am far from certain about this.