How does this LRC network meet rise time requirements?

Question

I found this LRC network and have been stuck trying to figure out how it satisfies the desired characteristics for impedance/rise time. A and B are the ±5V output from an HC4052 which require a rise time of 1.5±0.5us. The output impedance of this circuit should also be ~37.5Ω.

I can see that L/R*2.2 is 2us, but I can't figure out the purpose of the capacitor or how this meets the specified output impedance.

Edit: Schematic is from an article in EDN by Woodward

Answer 1

The cap+36 ohm resistor is an AC termination for the bus. Simplistically, it provides 36 ohm termination for high frequency components of the signal (like the edges) while not loading the bus in a DC standpoint.

Answer 2

Simple RLC circuits such as this are easily simulated. In fact, we have such a tool available at our fingertips (a button in the edit window), a schematic entry tool courtesy of CircuitLab:

^{simulate this circuit – Schematic created using CircuitLab}

You can see the waveform takes about 1.9µs to transition (10-90%), in the ballpark for the standard. The response is overdamped, with the RC time constant (1.7µs) perhaps dominating over the L/R (0.92µs). We can find the damping factor by solving the differential equation of the RLC circuit:
RLC circuit - Wikipedia

For a typical pure RC or RL system, rise time is 2.2 times the time constant, but this RLC combination is less fully-damped, and it happens that the rise time is somewhere inbetween these values. There is also a minor speed-up effect due to the resistance not being lumped in a single R, but the cable connection is tapped between R1 and R2, and therefore sees a somewhat "sped-up" signal, combining some of L1's current with C1's voltage.

There are some concerns:

• According to this reference: ARINC 429 Everything You Need To Know (Ultimate Guide) | Logic Fruit Technologies, a transmitter differential impedance of 75±5Ω is required, or 37.5Ω per pin.
• The CD74HC4052 however specifies only 40-45Ω typical. It can be perhaps 20-50% lower than that in practice (the minimum is not specified!); the maximum is specified as 120Ω (or even worse over temperature range). Logic devices unfortunately are not well specified: the wide tolerances ensure high production yield, but make them problematic for analog interface applications like this. Typical parts will meet the spec, but this can only be ensured in production by testing and sorting components prior to assembly.
• This internal resistance is expressed by R1 in the above circuit. I have selected the typical value, but you can adjust it in the simulation to see its effect.
• I have also included R3 and C2 to allow a very rough model of cable length and capacitance. A basic RLC equivalent suffices to model short cables (for this risetime, up to about 100m in length). According to the above reference, a bus up to about this length might be considered maximal, for which we might have values R3 = 5Ω and C2 = 12nF; a series inductance of 33µH might also be added to better represent it. (The values shown above are small enough to be irrelevant for simulation purposes, or if you like, are equivalent to about a meter of lossy cable.) This is still fairly small in comparison to C1, so the waveform is not expected to change much, but the change will be visible at such lengths, and reflections in longer cables set a clear limit around this value.