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I drew an AND gate as follows which mimics this diagram:

and gate

(source)

I understand how current flows between A and B(when both inputs are logical 1) because there is difference of voltage, maybe 6V, and AFAIK A and B are possibly connected making a circular circuit(at least via earth).

But I don't understand how current can flow from some signal sources to two transistors to manipulate transistors. There seems no difference of voltage regarding i1 and i2. I want to know the entire circuit diagram including the signal sources.

PS. Are there 3 separate circuits containing i1, i2, A-B, respectively?

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  • \$\begingroup\$ @PhilFrost he needs 10 rep before he can use the schematic editor. \$\endgroup\$
    – The Photon
    Jun 18 '13 at 16:26
  • \$\begingroup\$ You can edit your post to include that picture. \$\endgroup\$ Jun 18 '13 at 16:32
  • \$\begingroup\$ Current won't flow between any points if the voltages are equal (logical 1 e.g.) and anyway current won't flow between the inputs of a AND gate whatever the logic levels or difference in voltage levels. Maybe you could start by explaining what you think you know. A and B are not connected and don't make a circuit. Have you tried googling the circuit of an AND gate? \$\endgroup\$
    – Andy aka
    Jun 18 '13 at 16:33
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You mention:

But I don't understand how current can flow from some signal sources to two transistors to manipulate transistors. There seems no difference of voltage regarding i1 and i2. I want to know the entire circuit diagram including the signal sources.

So, if I understand correctly, you are confused as to how the inputs to the base of the transistors work. I will answer this.

The connection to the base of the transistors are left ambiguous because there are different applications possible to activate each transistor. For instance, you could use manual switches connected to a voltage source or a micro-controller to control the base pins. They are also left ambiguous so the focus is left to the logic of the circuit, and not how it is set up.

However, you were curious as to how such a circuit could be created, so I drew a very primitive example (I assumed you have npn transistors).

schematic

simulate this circuit – Schematic created using CircuitLab

This could also be done with a micro-controller as I've mentioned before. You forgot to add R1 in your diagram that you drew, which is very important because otherwise, Vout will be fixed to GND.

When both switches are logic: '1', current flows through R1 and creates a voltage at the R1 node. When either switch is open, the respective transistor becomes inactive. No current will then flow through R1. When no current flows through R1, the voltage drop over the resistor is zero, therefore the voltage at the Vout node is zero.

I hope this helps, however, I'm unsure what you mean by are there 3 separate circuits for i1, i2 and A-B.

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  • \$\begingroup\$ Thank you for your answer and schematic. :) But, one more question: when two switches are closed current may flow through a part of wire containing power source(battery?), Q1, Q2, and R1(forming square). But what about the part containing R2, R4, SW1 and SW2? Does current flow through that part too? If so, what's the direction of the current? I can't imagine a current that doesn't form a circular form. :-p I simulated the circuit via the link in your answer, but I didn't answer myself the question. It gave me some values for I and V at a point of the circuit, but I couldn't interpret it well. \$\endgroup\$ Jun 19 '13 at 12:53
  • \$\begingroup\$ You are correct that most of the current will travel in the "square", but a small amount of current will travel through the switches, into the Base of the transistors. This is what will activate the transistors to allow current to travel from Emitter to Collector. The current through the switches into the Base will rejoin with the rest of the current and output from the Collector also. \$\endgroup\$ Jun 19 '13 at 13:12
  • \$\begingroup\$ This is not a very good AND gate. If SW2 is closed, Vout will be about 4.9V whether SW1 is open or closed. \$\endgroup\$ May 28 '14 at 14:40
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In the original diagram using NPN transistors:

enter image description here

You connect A and B to either 6V (logic 1) or Ground (logic 0)

When A and B are connected to 6V, a small base current flows from the 6V supply, through the 10K resistors, into the base, out the emitter to ground (and back through the power source).

This small base current turns on the transistors allowing current to flow from collector to emitter.

Because of the current flowing through the 4.7K resistor, the voltage at out is high (as determined by ohms law)

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One problem with the circuit as drawn is when the base of an NPN is used to control the emitter voltage, the transistor will start to switch off as the output voltage approaches a point about 0.7 volts below the base. Consequently, if the output of one AND gate such as you've drawn were fed into one of the inputs of another, the output of that second gate couldn't get within 1.4 volts of the lower input to the first. While AND gates such as you have drawn may be useful in some limited scenarios, they are only useful in cases where the level of input drive which is known to be available exceeds the level of output drive which is required.

Inverters, NAND gates, and NOR gates are somewhat better as logic building blocks, because--provided the input signal is above a certain minimum strength--the strength of the output signal will be independent of the strength of the input signal. One can feed the output of one such device into the input of another, feed the output of that device into the input of third, etc. to any arbitrary depth without the signals becoming so weak as to be unusable. With AND gates such as you've drawn, the signal drop on each gate is such that trying to go beyond even 2 or 3 would likely be problematic.

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