SR latch and flipflops

Question

I am doing the practical of an SR (NOR) latch. I am initially giving input s=0,r=0, then I power on the SR latch, I found that q=0 and q'=1. I did it several times by turning on and off the circuit with 0,0 each time the output changes. Some times q=0 and q'=1 and sometimes q=0 and q'=1.

My question is if there is no previous state, how the circuit decides its previous state was q=0 and q='1?
How it is possible if I put s=0,r=0 initially? Because there is no previous output initially?

Answer 1

The initial latch state depends on properties of concrete gates you use, one gate is manufactured with faster response than the other.

If the initial state changes after every power-on it is probably caused by power-on switch bouncing since it involves some randomness. Or the power supply capacitor wasn’t fully discharged. Or some circuitry you connected to latch like leds etc affect it.

There are many options how to set initial state like generate a short pulse to S or R during power-on. Or place a small RC to one of latch input.

Answer 2

Here is the Karnaugh "table" for FF made with NOR gates.

We can see that if inputs (R,S) are (0,0), the outputs "ending" can be (0,1) or (1,0).
Note that "rarely", outputs can be "oscillating" from (1,1) to (0,0) ...

There is only one case where the "ending" (Q1,Q2)=(0,0) (case (R,S)=(1,1)), and two cases ( (R,S)=(0,1) or (1,0)) where the starting has a transient (Q1,Q2)=(0,0) and finish with (0,1) or (1,0).