I know the basic differences between Mealy and Moore FSM (Finite state machine). What I want to understand is the following:

  • Pros and cons of using Mealy over Moore and vice versa
  • In which situation Moore is more suitable than Mealy and vice versa

The figures of merit for comparison could be latency, throughput, area (state encoding FF's), power etc.


2 Answers 2


From a discrete logic & HDL perspective:

  • Mealy machines (generally) have fewer states. Mealy machines change their output based on their current input and present state, rather than just the present state. However, fewer states doesn't always mean simpler to implement.

  • Moore machines may be safer to use, because they change states on the clock edge (if you are using DFF logic for present and next state), whereas Mealy machines are faster, because the state is dependent on the input. Thus, the state can change asynchronously. This comes down to predictability vs raw speed.

When it comes down to it, it's difficult to draw hard lines where one machine would always be better than the other.

It really comes down to the specific task at hand. Does one want to have a synchronous or asynchronous machine? Is speed paramount? Will there be potential unstable (bouncing) signals? Are both the inputs and present state readily available? The answer to each of these questions determines the type of machine that would work best.

It's worth mentioning that for a hardware implementation, Mealy machines require less hardware in their circuits, but when working with an HDL and RTL scenario, the actual amount of discrete hardware may not be terribly important.

  • \$\begingroup\$ Although a Moore machine can only sample inputs or change outputs on clock edges, I would think that a Mealy-machine design could be made similarly. While some might argue that such flops added to a Mealy machine would constitute part of the state machine's "state", I would posit that it's more helpful to regard a the state machine as only encompassing those aspects of state which are generated by the machine and feed back into it. Note that for ROM-based machines, applying this this distinction to input flops may be critical if the signals feeding those flops are asynchronous. \$\endgroup\$
    – supercat
    Commented Nov 25, 2013 at 17:47
  • \$\begingroup\$ If there is only a single flop between an asynchronous signal and a ROM address pin, metastability of that single flop can corrupt the entire system state even if its value in a given time step should only control one bit of state for the next time step. By contrast, if the input feeds a flop whose output feeds nothing but a second flop, 99.9999% of metastability events on the first flop will be safely absorbed by the second. \$\endgroup\$
    – supercat
    Commented Nov 25, 2013 at 17:50

Jay covered almost everything to answer your question. One 'advantage' of the Moore machine is that it can be implemented in a Look up Table or SRAM memory. If your implementation is on an FPGA, let's say.. this might sometimes make the decision easy for you.


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