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How would I estimate the minimum size of a custom IC whose size is pad-limited with a large number of pads?

(Pad-limited means that the minimum die size is dictated by the size of the inputs and outputs, not the core internal logic. )

For example, I would like to have a custom IC made that has 256 shift registers 63 cells each. Could anyone give me a ballpark estimate of how small the chip could be made and maybe even a rough figure for power consumtion? Thank you !

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    \$\begingroup\$ If you had enough money to purchase this custom IC, you'd probably also have enough money to have a full-time engineer on staff who could answer this question for you. \$\endgroup\$ – Phil Frost Jun 21 '13 at 18:53
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This is one of those questions that the more experienced people on this site dread. Not because it is hard to answer, it isn't. But because the fact that you asked the question in the first place indicates that there is a giant can of worms just waiting to be opened. And most of those worms are not technical worms. I think it is an important question to answer, precisely because it is a bad question and similar questions are asked quite often.

You don't want a custom chip. I don't know what you want to do with it. I don't know your application. But odds are very high that you don't want a custom chip.

For starters, this chip will cost you somewhere around $100,000 to $500,000 just to develop.

That's not even considering the cost of the chips themselves. Next, you will have minimum quantities. That will be somewhere in the neighborhood of 50,000 to 1 million chips a year. The cost should be relatively small. At 50K/year, expect the per chip price to be around $4/each. If you get up to 1 million/year the price should drop to about $1/each.

So even before considering the technical issues, you are out $300,000 to $5,000,000 in the first year. People who have that kind of money to spend know that they need to hire qualified people rather than asking the question themselves on a web site. So I am guessing that you don't have that kind of money to invest in this project. This isn't an insult, it is just the realities of custom chip making.

The other huge red-flag that I see here is that the question assumes that 256 shift registers is the correct solution to your design problem. It probably isn't the correct solution-- but I don't know the exact usage for this so I could be wrong. Even so, I have never seen an application where 256 shift registers is the solution (that couldn't be solved using something more reasonable).

Let's assume that you really do need 256 shift registers. There are solutions that don't involve custom chips. FPGA's, for example. Depending on your clocking and I/O Pin requirements, even a small FPGA can do what you ask. It is even possible to do that in an FPGA that costs less than $5. If your volumes are less than 50K/year this is much cheaper than going the custom chip route (once you factor in your NRE).

Here's my suggestion: Write a different question that says what your design problem is and asks for a possible solution. I am talking about the design problem that is currently solved by lots of shift registers. Don't assume that you know what the solution is, leave that open. Then maybe we can offer a suggestion that is more realistic than custom chips.

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  • \$\begingroup\$ Somehow, that was a highly enjoyable read ;) Bam! \$\endgroup\$ – Rev1.0 Jun 21 '13 at 19:27
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I agree with David's post, but I was curious enough to run the calculations.

First off, it depends on if you want all 256 shift registers clocked simultaneously, or if you want to clock each one independently. I'm assuming you want to clock them all simultaneously, and that you're only interested in feeding the input, and seeing the output. Basically, it would be a 256 bit wide, 63 clock delay.

In terms of inputs and outputs, we have 256 inputs, 256 outputs, a clock, a global reset, and the power and ground pins. If I say 5% of the pads should be power and ground, then that gives us 13 power and ground pin pairs, which is about as light as I think I would go. This gives us a whopping total of 540 pins!

Since you said you wanted the smallest chip possible, I'm going to assume that we are pad-limited. This means that the limiting factor of the size of the chip is the number of inputs and outputs, not the size of the logic core. This makes the calculation possible because packaging is relatively process independent. A 63-stage shift register is not really that big, and we can always justify the pad-limited nature of the design by moving to a smaller process node. You could probably do this with a 350um process, so not that expensive (relative to other processes).

Since we are pad-limited, let's start talking about pad sizes. A "reasonable" pitch for pads is roughly 90um. Let's estimate the distance from a corner to first pad as 100um. If we say that you have a single row of pads, that would give you a side length of: $$\dfrac{540}{4} \times 90\mu m + 2\times 100\mu m= 12.35mm$$ We may be able to make things a bit better by using two rows of pads. We have to stagger the pads, so we don't quite get twice as many pads as a single row. This gives us an approximate side length of: $$ \dfrac{\dfrac{540}{4}+1}{2}\times90\mu m + 2\times 100\mu m= 6.32mm$$ A further option is to use C4 solder bumping. If we say that the solder bumps have a pitch of 200um, and that all our logic will fit around the pads (fully populated), we could have a 23 x 24 grid of solder bumps, giving a long-side dimension of: $$ 24 \times 200 \mu m + 2\times 100\mu m= 5.0mm $$

Note that this is purely for the physical die. If you wanted the die packaged in a BGA with 1 mm pin pitch, then a 24 x 24 BGA would be maybe 25mm on a side. Commercially available FPGAs can be had in slightly larger packages. This 27 x 27 BGA packaged part would only run you $65, and you would be able to buy about 150 of them before you break even on just the cost of a fabrication run.

For power consumption, with that many outputs, your power consumption will primarily be dictated by the capacitive load on each output. You could estimate that by finding the average capacitive load, your supply voltage, and the average output switching frequency. $$Power = C_{avg}V_{DD}^2f_{switch}$$

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