Problem: A simplified schematic of an oversampling circuit is shown below. A data sequence, \$x[n]\$, is transmitted by REG1 which is in clock domain \$C_{tx}\$. \$x[n]\$ is oversampled by REG2 in the clock domain \$C_{rx}\$, resulting in the sample sequence \$y[m]\$. The clock \$C_{tx}\$ has frequency \$f_{tx}\$ and the clock \$C_{rx}\$ has frequency \$f_{rx}\$ and the oversampling rate is defined as \$ \beta \in \mathbb{R} \$.
simulate this circuit – Schematic created using CircuitLab
Definitions:
- \$n = 0,1,2,\ldots \$
- \$m = 0,1,2,\ldots \$
- \$ \beta = f_{rx}/f_{tx} \$
Question:
What is \$y[m]\$, expressed in terms of \$x, n, m\$ and/or \$ \beta \$? Assume \$ \beta \geq 1\$. Also, REG1 and REG2 may be treated as zero-delay models: \$T_{propagation} = T_{setup} = T_{hold} = 0\$. For simplicity, you may assume \$\phi_{tx}(0) = \phi_{rx}(0) = 0\$, where \$\phi_{tx}(t)\$ is the phase of \$C_{tx}\$ at time \$t\$, and \$\phi_{rx}(t)\$ is the phase of \$C_{rx}\$ at time \$t\$.
All answers are welcome, but the accepted answer must provide analytical proof of the proposed expression. Intuitive explanations or a few evaluated cases are not analytical proof.