Can a system task like $display be used in code in Quartus II? I started learning verilog recently and I tried this simple code: module hello_world ; initial begin$display ("Hello World by jai");
#10 \$finish;
end

endmodule


Then, I set this module as Top_Level Entity, and clicked Analysis and Synthesis. Then comes the error:

Error: Can't synthesize current design -- Top partition does not contain any logic.

How can I use these tasks in Quartus, or can they be only used in software where we can write testbench (like Xilinx ise)?

I'm using Quartus II 9.1sp2.

• Do you know that this code can not be synthesized, so so what ate you trying to do with this? – FarhadA Jun 23 '13 at 21:38
• While these statements are not synthesizable, major FPGA vendors do offer a scheme which you can compile in to monitor values of the running design via the programmer cable, as a sort of built-in logic analyzer. – Chris Stratton Jun 28 '13 at 15:39