I started learning verilog recently and I tried this simple code:
module hello_world ; initial begin $display ("Hello World by jai"); #10 $finish; end endmodule
Then, I set this module as Top_Level Entity, and clicked Analysis and Synthesis. Then comes the error:
Error: Can't synthesize current design -- Top partition does not contain any logic.
How can I use these tasks in Quartus, or can they be only used in software where we can write testbench (like Xilinx ise)?
I'm using Quartus II 9.1sp2.