Say I instantiate a parametrized number instances in an array and each of these instances produces an 8-bit output value if it is selected. What would be the best way to wire these outputs together?
I currently use tri-state buffers as in the following example:
module foo(output wire [7:0] out); parameter N = 4; bar bars[0:N-1] (.out(out)); endmodule module bar(output wire [7:0] out); wire selected = ...; wire [7:0] value = ...; assign out = selected ? value : 8'bz; endmodule
Here the logic ensures the
selected signal will be
1 for one and only one instance.
This all works fine in the simulator as well as in an FPGA. However, since I get warnings about this construct while synthesizing and, as I understand, Xilinx removed internal tri-state buffers in newer FPGAs, I was wondering what the preferred way is to connect these output buses together.
I was thinking about changing the output assignment to
assign out = selected ? value : 8'b0;
and then OR-ing the outputs together. However, I'm not sure how to do this since the size of the OR-gate depends on a parameter.