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I am trying to build a T flip-flop from a D flip-flop. The D flip-flop looks like this enter image description here

and the simulated waveform shows that it works.(when there is a rising edge D will be passed to Q) enter image description here

So I started building a T flip-flop by connecting Qnot to D (I am expecting every clock rising edge Q will be toggled because Qnot is passed to Q) enter image description here

but the simulated waveform looks like this enter image description here

Q will oscillate when CLK is low. One oscillation period is around couple ns. I played with different Clear and Preset signals but it still happens.

If anyone can point out my errors. Thanks.

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    \$\begingroup\$ The first thing is not a FF, it's a latch. \$\endgroup\$ – avakar Jun 24 '13 at 20:06
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The first schematic shows a latch rather than a D flip-flop -- it forwards D to Q when CLK is high. Q maintains its value for CLK low.

This would almost explain the behavior of your latter circuit. Q should remain constant when CLK is low. It will forward !Q when CLK is high and therefore oscillate.

Why the oscillation happens with CLK low I cannot explain (perhaps the two screenshots are inconsistent?).

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  • \$\begingroup\$ The first circuit is indeed a latch. Sorry I was confused. But I took the screen shots after I compiled two circuits with no errors. Still struggling with the oscillation. \$\endgroup\$ – Timtianyang Jun 24 '13 at 21:08
  • \$\begingroup\$ So would Q oscillate when CLK is high because !Q is passed to Q continuously as long as CLK is high? It looks like I cannot build a T flip-flop from it then... \$\endgroup\$ – Timtianyang Jun 24 '13 at 21:12
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When the clock is HIGH there seems to be a race hazard through the circuit which causes a rapid oscillation.

Lets assume the starting condition is Q = 0 (NOT Q = 1)

enter image description here

when the clock signal goes HIGH

                        a b c d e f g
                        1   1 0 

g will go low causing d to go high causing c to go low causing g to go high and so on and so forth

when clock is low

                        a b c d e f g
                        0   1 0

f is low, b is high, c is high the system is stable

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  • \$\begingroup\$ Thanks for walking it through. Your analysis is right. My implementation to build a T flip-flop is incorrect because the toggle happens too much when CLK is high. \$\endgroup\$ – Timtianyang Jun 24 '13 at 21:21
  • \$\begingroup\$ Timtianyang - your very welcome, good luck with you next implementation \$\endgroup\$ – JIm Dearden Jun 25 '13 at 7:27

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