In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and outputs.

At the moment, my compiler (Quartus II) is not complaining when I mix I/O signals associated with clk1 with I/O signals associated with clk2. This is bad because the signals need to be synchronised when crossing clock domains.

What is the best way to constrain I/O signals to an associated clock? I have seen the SDC commands set_input_delay and set_output_delay, but I have set all the delays to 0 and I fear this might be the wrong way of doing it.


It is not an 'error' to sample data from one clock domain in another. Quartus will not prevent you doing it at design entry/synthesis stage. When you later run timing analysis with quartus_sta you will find that the register path between the two clocks (if truly different) is unable to make timing.

You are running timing analysis, right?

  • \$\begingroup\$ Yes, I'm running timing analysis. I'm just wondering how to make the register path between the two clocks "make timing" in a graceful way. At the moment I'm using set_false_path but that may be a little too aggressive. \$\endgroup\$
    – Randomblue
    Jun 28 '13 at 15:54
  • 1
    \$\begingroup\$ set_false_path is the accepted technique. This gives the fitter complete freedom in the routing of the path - if it decides a few trips around the peripheral of the chip is required, so be it. \$\endgroup\$
    – shuckc
    Jul 1 '13 at 13:16

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