In my Verilog design, I have two asynchronous clocks,
clk2. Associated with each clock is a bunch of inputs and outputs.
At the moment, my compiler (Quartus II) is not complaining when I mix I/O signals associated with
clk1 with I/O signals associated with
clk2. This is bad because the signals need to be synchronised when crossing clock domains.
What is the best way to constrain I/O signals to an associated clock? I have seen the SDC commands
set_output_delay, but I have set all the delays to
0 and I fear this might be the wrong way of doing it.