4
\$\begingroup\$

Question 1: When one interrupt handler is executed, will it be interrupted if another interrupt with the same priority occurs?

Question 2: When one interrupt handler is executed, will it be interrupted if another interrupt with the lower priority occurs?

I used MSP430. The interrupts are always nested as long as GIE is enabled. The priority is only determine whose interrupt handler is executed first if there are a few interrupts occurred at the same time and pended (before they are responded). But I don't find any answer for Cortex-M0 in its documents and google search.

\$\endgroup\$
2
  • \$\begingroup\$ Get DUI0497 Cortex-M0 Devices Generic User Guide. \$\endgroup\$
    – starblue
    Jun 28, 2013 at 7:52
  • \$\begingroup\$ Thanks, starblue. Just see your comment. You're right. This doc explains to all my questions very clearly. \$\endgroup\$
    – hailang
    Aug 8, 2013 at 22:44

1 Answer 1

3
\$\begingroup\$

The part that handles these things in a Cortex is the Nested Vectored Interrupt Controller (NVIC).

Question 1: When one interrupt handler is executed, will it be interrupted if another interrupt with the same priority occurs?

No, an interrupt will be acknowledged if it has a higher priority

Question 2: When one interrupt handler is executed, will it be interrupted if another interrupt with the lower priority occurs?

No, not while the interrupt handler is running.

\$\endgroup\$
5
  • \$\begingroup\$ Thanks for your answer, Wouter. infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/… Pre-emption: New exception has higher priority than current exception priority or thread and interrupts current flow. This is the response to a pended interrupt, causing entry to an ISR if the pended interrupt is higher priority than the active ISR or thread. When one ISR pre-empts another, the interrupts are nested. \$\endgroup\$
    – hailang
    Jun 28, 2013 at 13:21
  • \$\begingroup\$ Thanks for your answer, Wouter. In the link below, it is mentioned: infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/… Pre-emption: New exception has higher priority than current exception priority or thread and interrupts current flow. This is the response to a pended interrupt, causing entry to an ISR if the pended interrupt is higher priority than the active ISR or thread. When one ISR pre-empts another, the interrupts are nested. \$\endgroup\$
    – hailang
    Jun 28, 2013 at 13:32
  • 1
    \$\begingroup\$ Does this mean that the new exception always has higher prioirty than current one, so the currnt one will be pre-empted no matter theirs designated priorities? \$\endgroup\$
    – hailang
    Jun 28, 2013 at 13:35
  • \$\begingroup\$ Supplement: “2.3.5 Exception priorities” in <DUI0497A_cortex_m0_r0p0_generic_ug.pdf> has good information. \$\endgroup\$
    – hailang
    Aug 8, 2013 at 22:41
  • \$\begingroup\$ Test results: Same interrupt can’t preempt the running one. \$\endgroup\$
    – hailang
    Aug 8, 2013 at 22:41

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.