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I am using Indexed Vector Part Select in a Verilog test case and i am very confused with this.

when we have described

input [415:0] PQR_A;
output [63:0] ABC;

then is it valid

assign PLA=PQR_A[44*8 +: 64]

because i think in this way the bits will be from 352 to (352+ 64) i.e. 416, which is not valid

I know this is quite silly to ask that what is [0:7], it means 0,1,2,3,4,5,6,7 i.e. 8 bits.

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3 Answers 3

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Indexed vector select w[x +: y] has width y. The equivalent regular select is w[x : (x+y-1)] .

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  • \$\begingroup\$ Code has little endian notation, so first answer is right \$\endgroup\$
    – Prash N
    Commented Dec 24, 2015 at 14:15
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one line explanation of that is :

w[x +: y] == w[(x+y-1) : x ]

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I think it should be like this: w[x +: y] == w[(x+y-1) : x ]

For example:

a_vect[ 0 +: 8] == a_vect[ 7 : 0]

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    \$\begingroup\$ Can you elaborate why your answer has the order flipped from the already accepted answer? \$\endgroup\$
    – Adam Head
    Commented Aug 8, 2014 at 21:01

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