The title says it all in signal switching applications - besides choosing a different device, how can I reduce the turn-off delay of (N-channel) MOSFETs? Is there something similar to the Baker Clamp used for BJTs?

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    \$\begingroup\$ It might help if you state which FET, how you are driving it FET now. \$\endgroup\$ Jun 29, 2013 at 21:13

4 Answers 4


A MOSFET gate and driver look something like this:


simulate this circuit – Schematic created using CircuitLab

\$C_G\$ is mostly the gate capacitance of the MOSFET itself. The driver may add some capacitance of its own, but it's usually negligible.

\$L_G\$ and \$R_G\$ mostly come from the gate driver circuit. The leads of the MOSFET also contribute, but to a lesser degree.

\$R_G\$ is also expressly added in some driver circuits to dampen the resonance of \$L_G\$ and \$C_G\$. Without this damping, ringing can result in the voltage at M1's gate taking transient excursions well beyond the voltage provided by \$V_{GS}\$, sometimes exceeding the maximum specified by the MOSFET and damaging the gate.

For the fastest possible switching times, you want all of these to be as little as possible.

Minimizing \$R_G\$ is pretty straightforward. Don't add any more resistance than required, and don't make the PCB traces excessively thin. You also want the driver to be as close to the MOSFET as possible, and you want it to be something capable of sinking and sourcing high current. The simplest way to do that might be to add a BJT push-pull pair of emitter followers:


simulate this circuit

For a more complex example, see driving low side of a mosfet bridge with 3.3V. Of course, there are also integrated solutions.

If it's more important to have fast turn-off than fast turn-on (common in H-bridge applications), then D1 can be added to mostly bypass \$R_G\$ during turn-off, while still retaining much of the damping capability.

To minimize \$L_G\$, be mindful of not only the length of the gate trace, but also the return path from the source back to the gate driver. Remember, the gate charging current must flow through the gate and the source, and back to the driver. The inductance of this loop is proportional to the area it encircles, and at high frequencies, this inductance will limit the switching speed much more than the resistance \$R_G\$. Common layout practice is to have a solid ground plane under the MOSFET and the driver, with the gate trace as short as possible running over this. Where you need to connect layers with vias, include several, if possible, to minimize their effective inductance.

Remember also that \$L_G\$ and \$R_G\$ include the power supply impedance. Be sure the gate driver is adequately supplied with power supply decoupling capacitors. Use several, in parallel, to maximize the capacitance and minimize the inductance.

\$C_G\$ can't be directly reduced, except by selecting a different MOSFET. More expensive MOSFETs can deliver less gate capacitance for a lower \$R_{DS(on)}\$ or maximum current handling ability. Also, don't use a MOSFET with more current handling ability than necessary; you will pay for it in increased gate capacitance.

Most gate driver designs can also benefit from driving the gate to a negative voltage. By applying a higher voltage to \$L_G\$ and \$R_G\$, the current will become greater, faster, leading to a higher \$\frac{di}{dt}\$ and thus faster turn-off. Also remember that the higher you make \$\frac{di}{dt}\$, the faster you can switch, but also the worse ringing will be.

Also, keep in mind that if you succeed at achieving a very fast turn-off, you may bump into your MOSFET's \$\frac{dv}{dt}\$ limit. As the drain-source voltage increases, the drain-gate and drain-body capacitance must be charged, and this means the gate driver must sink that charging current. If it can't, then the gate voltage may rise enough to turn the MOSFET back on, and depending on your circuit, something bad could happen. Usually this means shoot-through for H-bridges.

schematic of MOSFET parasitic capacitances

from International Rectifier - Power MOSFET Basics

This is another reason to include D1 if you've intentionally added \$R_G\$.

The concept of a baker clamp can also be applied to a MOSFET, simply by not driving the gate to a higher voltage than necessary. However, unlike BJTs, MOSFETs experience a decreasing \$R_{DS}\$ as \$V_{GS}\$ increases, so there is some value in raising \$V_{GS}\$ above the turn-on threshold.

on-resistance vs gate voltage

an example, for 2N7000

You will have to calculate your thermal limits to see if you can gain something here, but I'd say if \$R_{DS}\$ is low enough that you don't need to drive the gate very high, you'd get better performance by selecting a different MOSFET with lower overall gate capacitance and higher \$R_{DS(on)}\$. This is because most of the charge you have to move, and thus time you have to wait to turn on or off, is spent when the gate voltage is crossing the threshold voltage \$V_{th}\$:

gate charge characteristics

2N7000 again. The flat section in the middle is at \$V_{th}\$.

Increasing the gate voltage above \$V_{th}\$ takes relatively little charge, but you can get substantial reductions in \$R_{DS}\$.


Not trying to compete with Phil's answer, because it is really good. But, a couple of things to think about.

You don't mention what kind of part you are using, but if you really need to reduce turn-off delay you might need to use a surface mount part. A part in a TO-220, for example will have built into the package 7nH of inductance and as much as 10 Ohms of gate resistance that you can't do anything about. While a surface mount part would have more like 3nH inductance and 3 Ohms gate resistance, which could be switched a lot faster.

As far as pulling charge out of the gate faster, you could consider adding a pnp pull down transistor at the gate of the FET. Something like this:

enter image description here

The transistor Q5 acts as a local low inductance pull down that divides any upstream gate circuit resistance by transistor \$\beta\$. This is kind of like Phil's idea of using the diode, except you get the benefit of the gain.

If you would like quantitative guidelines to finding the minimum gate resistance that should be used you could look at this post.


There are a number of things you can do to speed up turn-off for a MOSFET.

1) Use a lower impedance gate driver that is capable of discharging the gate capacitance faster.

2) If you have a resistor in series from the gate driver to the gate try lowering the value of this resistance some.

3) If there is a resistor in series with the gate from the driver try putting a capacitor across this series resistor. This can speed up the FET turnoff provided the driver has a low enough impedance and the R/C time constant of the resistor/capacitor pair permit the capacitor to be discharged before the on to off transition.

4) Try biasing the gate driver for the FET so that the gate swings a small amount below the source voltage during and after the off transition of the gate. If the source is at GND then try to get the gate a few hundred millivolts below GND.


Apart from what Michael Karas says there's no point in applying more gate voltage than what you need. This, in a roundabout way is what the baker clamp does to a BJT.

So, you find that to adequately turn the FET on you need (say) 5V but you apply 10V - 5 of those volts have to be "discharged" before the FET begins the turn-off phase.

It's "easy" with a BJT to automate this with diodes but if you can select exactly how much gate voltage you need to apply (circuit board dependent) and take into account temperature and other things (that may mean you need a volt or two more), then you might be saving a few nano seconds.


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