How to place decoupling capacitor in four-layer PCB?

Question

I searched a technology document about placement of decoupling capacitors and the main idea is shown in the following picture:

I think it is reasonable but do I have to put the decoupling capacitor and MCU in the same layer? it is not convenient for me to place other devices. So i choose to place the decoupling capacitor in the bottom layer

My PCB is a four-layer(signal-power-gnd-signal) one and when I split power and gnd layers the two vias closing to the pins of MCU in the above picture will not be included in net of power and gnd layer. Does it have the same nice performance as the case f in picture one? Do i have to take of inductance of vias in this case?

Answer 1

This is a complex problem to analyze and many parts of it only are important when you run into a problem at a specific frequency on a specific product that noone knows how to fix.

While this answer is sort of a side point, it addresses some assumptions. We are talking about bypass caps which only concern is high frequency noise and not large power draws. High frequency noise is best dealt with using monolithic ceramic caps (ESR less of a concern as it is just your minimum impedance achievable). Larger power fluxes need bigger tantalum caps. See the frequency performance here:

You can use the SFR (self resonant frequency) to your advantage. If you have a problem with say a 1GHz clock leaking through, you can start by adding another bypass cap that is self-resonant a little higher than 1Ghz. 0402 10pF (from experience, not from the graph) are pretty self-resonant around 1Ghz.

However this is only part of the story. What happens at higher frequencies? The mounted inductance plays a role and that is where the layout also comes into play between the layers in the board. For example a power layer and ground layer in the board with an SMD cap has the following mounted inductance loop model -- shown in red:

In an example of 2 planes (power/gnd) in FR4 you can see that at high frequencies even the mounting of the capacitor can make a big difference. The black trace is without the cap. The blue and red show two different mounting topologies that show different mounting inductances.

The anti-resonances can cause more problems at high rates. And you might think you don't care about 1GHz+ noise, but the FCC might, and if you want clean edges on your digital 500Mhz signals, then you're going to need a lot of harmonics for that square wave. For example a 100Mhz clock to have a 0.5nS rise time needs at least a 900Mhz harmonic.

So what about the package itself? You've got output drivers, input pins, bonding wires, ground pins, power pins...(fyi ecb=pcb)

A full model would look something like this (including cross-coupling effects). The cavity plane is where the die would be represented. (Ignore the part with the Equivalent L+R for package Bypass Cap--that bit for a ic bonded with some on board bypass which isn't the case for this question).

Using microwave probes, a high frequency network analyzer and special TDR calibration fixtures the impact of the package both in terms of power/ground planes and cross coupling can be estimated.

Now on top of all that we have your question of where to put the cap. I found a nice article by Howard Johnson who shows how to do a model of the system and how to analyze and measure it. Here's an example layout and how to look at each part and optimize it.

Unfortunately the presentation doesn't go over your specific case of IC to vias or IC to cap to vias. You could play with the model and see which provides more bypass but remember the cap effects, and the power to ground plane coupling. My bet is if the chip is your noise source minimizing all inductance between the die and the cap would provide the best results assuming the vias for the cap are also near and symmetric like Case F.

EDIT: It occurred to me that I should summarize all this info. From the discussion you can see that there are many aspects of high frequency work that requires careful consideration:

• type of capacitor chosen (package size, material and value)
• the capacitance and anti-resonance of the Power-Ground plane itself
• the capacitors mounting inductance (there are special SMD high frequency cap packages like ICD/X2Y)
• digital designs need a surprising amount of high frequency harmonics
• IC packaging type
• lastly the layout

Case F optimizes the above layout model of the uC noise source by \$L_2=L_4=0\$ and \$L_1=L_3=minimum\$.

From the comments in the discussion with David about BGA's where placing the bypass on the back side of the board with vias can be ok and often the optimal choice. This is because even though \$L_2=L_4\ne0\$ you can really reduce \$L_1=L_3=small\$ and the overall solution is better than making long traces to the bypass cap without using vias. In addition the BGA package style has less inductance which helps with bypassing.

In addition this model shows why the layout should be symmetrical as possible to make the bypassing cap most effective to reduce both ground bounce and supply spikes by keeping both ground paths and power paths as similar as possible.

Answer 2

Your goal in placing the capacitor is to reduce the AC impedance of the supply rails. You want to do all of these things:

• minimize resistance
• minimize inductance
• maximize capacitance

Assuming the trace lengths are reasonably short and thick, the resistance will be negligible relative to the inductance. Adding more capacitance is easy. Minimizing inductance is the hard part.

Calculating inductance exactly is complex, but there's a rule of thumb that's simpler: inductance is proportional to the area enclosed by the loop in which the current flows. Since at high frequencies, the inductance (not the resistance) of the power rails is the more significant impedance, your goal is to make sure the inductance through the decoupling cap is lower than the inductance through everything else. Ideally, by a large margin, since what you are essentially making is a filter that attenuates high-frequency noise generated by the IC to the power supply rails.

^{simulate this circuit – Schematic created using CircuitLab}

If you place C1 on the bottom, then you are adding more inductance at L3 by requiring the noise current to go through vias. It's worse than having it on the top, but is it good enough? It will depend on your application and how much noise you can tolerate.

If you are going to have four vias as in your proposed layout, it would be better to have all four connected to the power planes. Also, get them as close to the pads as you can, such that you don't even need traces to connect them. This will minimize the overall inductance. You don't need to worry about making the noise currents go "past" the capacitor. The inductance of the supply rails (L2) will force the high-frequency current to do that, since the rails are so much bigger and have so much more loop area. Instead, focus on minimizing the inductance to your capacitor (L1, L3).

Also, keep in mind that although increasing L2 would improve the filter, if you do it by moving the vias connecting the capacitor to the power planes far away (as in your example F), then you are doing it by including a loop antenna in your layout. This will give you worse EMI performance and worse ground bounce. If you must add impedance here, use a resistor or an inductor with low leakage. Rarely would I think this is necessary however: inspect some very high-speed layout like a PC motherboard around the CPU, and you won't find any L2 or R2 beyond what's unavoidable and intrinsic to the layout. If you are going to add another component, why not add another decoupling capacitor, which will double the capacitance, and halve the undesired inductances?

Answer 3

The electric charges flow through many paths.

I try to picture the path that the electrons travel each time the chip pulls a pulse of power through a pair of power pins -- one positive, the other GND. For each capacitor on the entire board, electrons travel in a closed path (a circuit) from that capacitor through some path to one power pin, and out the other power pin back to the same capacitor.

The total loop area of that closed path is proportional to its inductance.

The paths with less impedance will automatically carry more of the charges. As long as you provide at least one path with low impedance, the charges will automatically take advantage of it.

If that path includes some wide conductor like a ground plane, there are many possible paths through that plane. At the beginning of the pulse the charges will automatically take advantage of whatever particular path through that conductor will minimize the loop area and minimized inductance -- this is a good thing.

I had one PCB where the capacitors for the ADC were on the opposite side of the board from the ADC. I measured significantly less noise after I took off those capacitors and kludged added capacitors to the power pins of the ADC on the same side of the board. My understanding is that the improvement is entirely due to eliminating the via inductance.

the two vias closing to the pins of MCU in the above picture will not be included in net of power and gnd layer.

There seem to be 4 cases.

1. The capacitor sits across the IC power pins on the same side of the board. The loop goes from the capacitor, in one power pin, out the other power pin, back to the capacitor. For most chips, this gives the least loop area, minimizing inductance.
2. The capacitor sits on the opposite side of the board, and the 4 vias between it and the chip are connected to the power and GND planes. The loop goes from the capacitor, through 2 vias in parallel, in one power pin, out the other power pin, through the other 2 vias in parallel, back to the capacitor.
3. The capacitor sits on the opposite side of the board, and the 2 vias between it and the chip are connected to the power and GND planes. The loop goes from the capacitor, through one via, in one power pin, out the other power pin, through the other via, back to the capacitor.
4. The capacitor sits on the opposite side of the board, and the 2 vias between it and the chip are carefully isolated from the power and GND planes. 2 other vias connect the capacitor to the power and GND planes. Isolating vias so they don't connect to the power or GND planes can only increase the total net impedance, making ground bounce worse -- I can't see any reason to ever do this.

(2) and (4) have the vias arranged in exactly the same locations, occupying exactly the same space.

Some high-speed digital devices and some high-precision analog devices require you to use (1) -- the other options won't work at all. Such devices will usually specifically mention this in the data sheet.

Some devices will work adequately with options (2) or (3). They have worse ground-bounce and worse EMI/RFI/EMC, but if the result is still well below the FCC limits and works adequately, it may be worth it in order to make routing simpler.

EDIT:

Stevan Dobrasevic. "Freescale Semiconductor AN2127/D: EMC Guidelines for MPC500-Based Automotive Powertrain Systems" in "Figure 2 MPC55x Double-Sided Component Placement Application" recommends case 2: capacitors on the opposite side of the board from the processor, with the processor and the capacitors each directly connected to the positive and GND planes with multiple vias.

Decoupling is one of the least understood topics in engineering.

"Avoiding noise in a PCB" has some tips on avoiding noise on a PCB. In particular, "partitioning and layout of a mixed signal pcb" by Henry W. Ott shows exactly where the "noise currents" are located, explains why carefully isolating grounds sometimes makes things a little better, and how fixing the actual problem (and connecting all grounds together to make one solid ground plane) is the best. Carefully isolating a via (or any other part of the GND plane) from the GND plane is counter-productive.

Either (a) that path is the path of minimum inductance, and it doesn't matter if you carefully isolate that via from GND or not -- most of them travel the same path whether there is a connection to GND or not. Or (b) there is some other path that has a smaller loop area, hence less inductance, in which case carefully isolating that via from GND will make that inductance worse (bigger) and make EMC/EMI/RFI worse.

Answer 4

Placing a decoupling capacitor, few things:

1. It must be physically as close as possible the power pin of the IC.
2. Traces connecting the decap toPWR and GND vias must be thick and as short as possible.
3. Next comes whether should be placed at TOP or BOTTOM? the answer is decap must be placed close to the power plane, so that it can easily tap power can deliver to IC. Example: if Layer 2 from TOP is power plane place IC on TOP layer, if Layer 3 is power plane from TOP, place IC at the bottom layer.This point is only valid for asymmetrical PCB stack-up, as the loop area remains same for symmetrical stack-ups.
4. Since decaps also act as tank for storing charge, the less ESR(effective series resistance) value capacitors like Tantalum SMD, give better performance than through hole ones.