On some PCB designs, specific traces are routed in curious ways. This probably has to do with high frequency design considerations and general signal behavior that I am not familiar with.

Let's take this PCB (somewhere from the web) as an example. It shows part of a PCIe card with SATA routing and DDR2 RAM:

Example PCB

I highlighted 4 areas that qualify as unusual trace layout (from my perspective).

  1. What are those shapes supposed to achieve? How do designers come up with what pattern is required?
  2. Another example of wave shaped, antenna like routing.
  3. This is fairly rare. But obviously the designer deliberately avoided 45° traces. Why?
  4. Curves again and a single "pulse" within the trace. How can this have any significant effect?

So what are the use cases and benefits of this techniques?

I want to be able to take those into consideration when doing future PCB designs.

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    \$\begingroup\$ Related question: electronics.stackexchange.com/questions/4168/… \$\endgroup\$ – m.Alin Jul 3 '13 at 7:44
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    \$\begingroup\$ @m.Alin That's only a partial answer to this question. It's on the right track though. Doesn't address the curved traces. \$\endgroup\$ – Passerby Jul 3 '13 at 7:49
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    \$\begingroup\$ Guess: 1&4) equalise length of pairs of traces. 2) delay 3) avoid signal reflection at sharp bends. \$\endgroup\$ – RedGrittyBrick Jul 3 '13 at 8:12
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    \$\begingroup\$ @m.Alin: Thanks for the link. I didn't search for "squiggly trace" ;) As Passerby noted, this provides a partial answer. But maybe someone can post an answer with respect to the 4 mentioned examples and provide some additional information based on design experience. \$\endgroup\$ – Rev1.0 Jul 3 '13 at 8:14
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    \$\begingroup\$ @RedGrittyBrick deserves more love for that answer. \$\endgroup\$ – John U Jul 3 '13 at 9:11

1) Equalisation of length of pairs of traces

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From Board Design Resource Center

2) Delay (e.g. of clock for timing purposes)?

enter image description here

See also Adding delay intentionally

3) Reduce signal reflections due to discontinuities in trace width?

enter image description here
from Circuit Board Layout Techniques

See also How should I lay out timing matched traces?

  • \$\begingroup\$ Just to note, for 3, I'm assuming that we are not getting the whole picture. That's at least a double sided board. Some of these traces might be routed to avoid routing directly above/below a different set of noisy traces or components. \$\endgroup\$ – Passerby Jul 3 '13 at 11:08
  • \$\begingroup\$ The Document "Circuit Board Layout Techniques" looks like a nice read. Since it is labeled as "Chapter 17", I wonder what the other chapters are about. Do you have a link to the whole collection? \$\endgroup\$ – Rev1.0 Jul 3 '13 at 12:41
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    \$\begingroup\$ @Rev: ti.com/lit/an/slod006b/slod006b.pdf \$\endgroup\$ – RedGrittyBrick Jul 3 '13 at 12:43

This is not intended to be a complete answer rather it's a useful hint at what designers do when complex clock distribution is required. (courtesy of TI source) showing bad and good clock layout design : -

enter image description here

  • \$\begingroup\$ Interesting find. Do high end PCB design tools actually support automatic trace length comparison and maybe auto-serpentine routing to match the length etc.? \$\endgroup\$ – Rev1.0 Jul 3 '13 at 12:33
  • \$\begingroup\$ @Rev1.0 I believe they do. \$\endgroup\$ – Andy aka Jul 3 '13 at 12:40
  • \$\begingroup\$ Tools like Altium include automatic trace length measurement and serpentining. \$\endgroup\$ – Fix It Until It's Broken Feb 4 '15 at 17:38

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