On the 555 we have pin 6,2,3 with opamps but no feedback other than ground so I wonder how this can be connected at work OK because I see on Wikipedia it has 25 transistors but only 8 pins so maybe there are hidden connections to be made? Also only 3 modes are shown but no timer mode so maybe this is correct and something else must be done maybe some varying voltage on those pins do some function that is not in the documentation? Its amazing the chip has been around a long time but no information is provided.


closed as unclear what you're asking by PeterJ, Leon Heller, Olin Lathrop, Dave Tweed, Nick Alexeev Jul 6 '13 at 16:19

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    \$\begingroup\$ Of course documentation is provided, you've just not looked for it, eg. ti.com/lit/ds/symlink/lm555.pdf \$\endgroup\$ – pjc50 Jul 6 '13 at 10:18
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    \$\begingroup\$ which search engine did you type 555 into? I want to avoid it at all costs... \$\endgroup\$ – Spoon Jul 6 '13 at 12:39
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    \$\begingroup\$ Huh? Try breaking up separate thoughts into separate coherent sentences. And no, there is a lot of information about this chip out there, starting with the datasheet. What is amazing is that you weren't able to find any of it. \$\endgroup\$ – Olin Lathrop Jul 6 '13 at 13:23

Because they are comparator circuits not 'op amps'.

enter image description here

There are THREE 5K (555) resistors in form a potential divider inside the chip. This provides the 2/3 supply and 1/3 supply references to the two comparators.

Pin 7 is a discharge transistor for the capacitor.

Pin 5 is connected between two of the 5k resistors and allows for an external change or modulation of the trigger values.

All of this information has been around since the chips were first designed.

enter image description here

Consider the astable circuit.

Pin 8 is connected to the positive supply and Pin 1 is connected to 0V.

Pin 4 - Reset- is also connected to the positive supply to enable the 555 to function.

The capacitor, C1, initially has no charge (0V). On powering up it is charged through R1 and R2. As it is already below the trigger level the output of this comparator doesn't change as the voltage rises.

The output, pin 3, will be HIGH.

When the voltage across the capacitor reaches 2/3 supply the threshold comparator switches the internal latch to 'reset',

The output (pin 3) switches to LOW.

It also turns ON the discharge transistor (pin 7).

The capacitor now starts to discharge through R2. The voltage falls across the capacitor until it reaches 1/3 supply when the trigger comparator 'sets' the output (pin 3) to high and the discharge transistor is turned OFF.

The capacitor is now charged through R1 and R2 until it reaches 2/3 supply and the whole cycle is repeated over and over.

A small capacitor (usually about 0.1uF) is connected to pin 5 (control) to smooth out any spikes in voltage on the internal divider. (the 555 produces spikes of current when it switches so decoupling with capacitors is important for reliable operation.)

  • \$\begingroup\$ The documentation I've seen for the 555 is unclear about how it acts in cases where the "set" input on the latch is set simultaneous with one of the "reset" inputs, whether both reset inputs are equivalent in that regard, and whether all 555 derivatives have the same corner-case behaviors. Do you know of any definitive documentation on the subject? \$\endgroup\$ – supercat Oct 10 '16 at 14:49
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    \$\begingroup\$ @supercat You comment doesn't refer to the OP or the answer I give. What I suggest is you ask it as a stack question. However, IMHO, the documentation does give this information indirectly in that the external pin 4 (NOT reset) overides the internal set/reset signal which you can work out from the block and schematic diagram. Strictly speaking the trigger and threshold inputs are not actual (logical) set/reset inputs. Remember that the 555 wasn't designed as an SR latch, or even a 'digital' chip so the question of simultaneous 'reset' (a race condition) was of no concern. \$\endgroup\$ – JIm Dearden Oct 10 '16 at 16:12
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    \$\begingroup\$ I figured if you knew the answer it may not be worth bugging everyone with a question. Your diagram--like the data sheet--shows a black box with two R inputs and an S input, but doesn't say what's in the box or describe its behavior with all of the combinations of highs and lows; I was wondering if you knew of any good definitive documentation describing all the states. \$\endgroup\$ – supercat Oct 10 '16 at 16:20
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    \$\begingroup\$ @supercat The internal SR latch is buried deep inside the circuit but it is clear to anyone analysing the circuit that the external reset overrides the SR inputs. Take a look at this article sentex.ca/~mec1995/gadgets/555/555.html specifically at the description of the reset pin (pin 4). \$\endgroup\$ – JIm Dearden Oct 10 '16 at 16:29

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