# To what extent can an FPGA be “configured for desired use”?

If the title is off putting, I will elaborate.

Some say that if you want a custom CPU you can "customize" it with a field programmable IC, AKA, field programmable gate array.

But to what extent? And is over and under clocking, address line modding, register-level-transfers, and other features able to customize?

For example, one would expect a FPGA to enable "changeable", but changeable in the sense that it can be optimized for a specific purpose, speed, and system?

Like, if I want an FPGA to be customized to replicate an old video game system I would expect it to have a slower clock, less bit width, and to access slower DRAM.

Can FPGAs really be customized for a wide variety of uses, either under clocking and lowering performance, to over clocking and extending to maximum processing power and I/O lines, etc.?

• I think the main problem here is that you need to know the basics of digital design, to understand what a CPU is and how it is made, and then some basic knowledge of "logic" is before you get into what "programmable logic" is. If you don't know the basics of logic and how a CPU is made out of logic gates, then it is hard to explain what a PGA is. – FarhadA Jul 7 '13 at 9:02
• It's not uncommon for an FPGA to be able to do at 40 or 50MHz (e.g.) everything an old 8 bit processor could do at a mere 1 or 2MHz. So if you want to replicate an old system, you might take advantage of the FPGA's speed advantage, or it might be something you'd have to compensate for by dividing your clocks down. For example an ancient word processor might benefit, but a video game might become impossible to play. – JustJeff Jul 8 '13 at 2:24
• -1 Too general, open question. Can be "discussed", not "answered". – Philippe Jul 8 '13 at 9:19

To what extent can an FPGA be “configured for desired use”?

An FPGA contains certain resources, like flip-flops, programmable look-up tables (which can be configured to replicate the function of logic gates), block memory, and high-speed i/o transceivers. These resources are connected by a mesh of interconnect wires, which can be programmatically connected to the other resources.

You can configure the FPGA for your use exactly to the extent that you are clever enough to figure out how those resources can be used to produce the function required for your use.

This is somewhat simplified by the ability of synthesis tools to figure out how to allocate those resources when given a higher-level description of the function in a hardware description language (HDL). However even with the help of synthesis tools, a good FPGA designer will structure their code with the underlying resources in mind in order to maximize the functionality they can obtain from a given FPGA.

For example, one would expect a FPGA to enable "changeable", but changeable in the sense that it can be optimized for a specific purpose, speed, and system?

As others have said, there is generally a maximum clock frequency that a given FPGA can achieve. And the FPGA can generally operate from 0 Hz up to that maximum frequency.

What hasn't been mentioned yet is that the maximum frequency is only achieved when the combinatorial logic between one flip-flop and the next has a certain limited complexity, and when the design overall leaves enough resources free to give the design tool freedom to optimize the interconnects with a reasonable amount of computational effort.

If too-complex logic is used between flip-flops, or if the resources are highly utilized (say, more than 70% utilization) you'll likely find that the maximum frequency for your design is substantially less than the ideal maximum frequency for that FPGA.

Simplistic answer - an FPGA is a type of programmable logic device that (within certain constraints) can be used to replace a bunch of hard-wired TTL/CMOS logic. Because it pretty can much reproduce the original logic circuit (if you want it to) it can run at whatever clock speed the original would run at.

I would not say...

That if you want a custom CPU you can "customize" it with a field programmable IC, AKA, field programmable gate array.

That would be going too far. Do not confuse CPUs with FPGAs - they serve different applications but with some overlap.

• What are you saying? That a CPU is not an FPGA? – Bit Girl Jul 6 '13 at 21:16
• And what do you mean by this: "it can run at whatever clock speed the original would run at."? – Bit Girl Jul 6 '13 at 21:17
• CPUs are not FPGAs and if you design an FPGA to replace a standard logic circuit made from standard gates it will run at whatever clock speed you want from 0.00000000001Hz (basically DC or 0Hz) to over 100MHz (a lot will run faster of course). – Andy aka Jul 6 '13 at 21:22
• @BitGirl - You can implement a CPU using a FPGA, but you cannot implement a FPGA using a CPU. Basically, a FPGA is a bunch of configurable logic. As such, it can, very literally, be configured so that the programmable logic implements an entire CPU (Generally called a "soft-core"). – Connor Wolf Jul 6 '13 at 22:30
• @BitGirl - With regard to clock frequencies, most FPGAs (and CPUs too) have a maximum clock frequency. However, excepting certain types of RAM (DRAM), logic does not generally have a minimum clock rate, and this includes most CPUs. As such, the clock rate that a FPGA can support is generally 0 Hz <-> the maximum clock rate the FPGA hardware supports (the maximum rate will typically be documented in the FPGA's datasheets). – Connor Wolf Jul 6 '13 at 22:32

The answers here are fine but they make it seem like it is a lame pile of logic.

You can replicate games with a FPGA. Just get a board that has VGA and some buttons, switches, and I/O. I am currently working on a Pong game and am working out the collision detection at the moment. Since a FPGA can be super parallel you can drive the VGA while grabbing the input and changing the positions of the characters and do all the game logic.

I have barely used the RAM on my board but modules are easily enough created to read and write from it. One thing that can be annoying is that you can't hook up the RAM to multiple things like you would want. You need to add a arbiter (FIFO, round robin, etc) which lets each module read/write one at a time.

To answer a specific question. With a FPGA you can underclock with prescalers which is written in the code. Just to show you how easy it is to slow things down, here is some VHDL code to demonstrate a underclock. Just say that the FPGA clock runs at 100hz.

underclock: process(clk)
variable prescaler_count: natural := 0;
variable prescaler: natural := 10; -- 100 hz / prescaler = desired speed
begin
if rising_edge(clk) then

if count >= prescaler then
-- Do what you want at 10hz here...
-- main clk runs at 100hz. 100hz/10 = 10hz

count := 0;
end if;

count := count + 1;
end if;
end process;


The maximum clock is basically what you get and nothing can be done about that. Sometimes there are clock multipliers but I could consider that to be a part of the maximum. There is usually jumpers to change speeds.

Update:

After thinking about your words "configured for desired use" I realized I should talk about the constraints file. You do not have to use everything or all pins on your board for every application. You define what you want to use in the constraints file.

With an FPGA you can make (almost) ANY digital circuit without having lots of ICs with gates, latches, register, counters, etc. And you have the freedom of changing the functionality of that "programmed hardware" by just changing the FPGA configuration. These are the great points about FPGAs: freedom to design and freedom to reconfigure.

Now when talking about CPUs, as they are a collection of logic elements, can be replicated into a given FPGA, they are called soft processors or embedded processors. Xilinx offers one called microblaze, Altera does the same with Nios. Some people start from scratch and design their own processors/ microcontrollers, while others try to make clones of their favourites.

I would say the main reason for having an embedded processor is when the rest of logic is already in an FPGA, so why having it external? Some time ago I read about a guy replicating one of those first computers (Cray-1 or Cray-2 or similar) into an FPGA.