I am working with testing certain test cases with iverilog with -o option for example

iverilog -o <output file name> <Test bench if required> <verilog file>

I had also read about the other flags like -c -s and others given on this link, but i didn't get any test cases to test them.I am pretty new to verilog.So if any one can provide small test cases for iverlog to check other flags.

  • 1
    \$\begingroup\$ The manual may answer your questions if you haven't already checked iverilog.wikia.com/wiki/Iverilog_Flags \$\endgroup\$ – travisbartley Jul 8 '13 at 10:05
  • \$\begingroup\$ @trav1s: yes i had already checked that link but didn't find it that much useful.Searching for more. \$\endgroup\$ – shailendra Jul 8 '13 at 10:13

After studying further i found that -c option can be used even for two files i.e. testbench.v and verilog.v.

we just need to create a ".txt" file with the name of the both the files written line after line like this

testbench.v verilog.v

and pass it to iverilog.Further i wasn't able to get any test case with the usability of -s flag, though i tried to use it in followoing case but it gives no result and give wrong .vvp file which after executing produce no .vcd file.

module half_adder(
    output S,C,
input A,B


module full_adder(
    output S,Cout,
    input A,B,Cin
wire s1,c1,c2;
half_adder HA1(s1,c1,A,B);
half_adder HA2(S,c2,s1,Cin);
or OG1(Cout,c1,c2);


module ripple_adder_4bit(
    output [3:0] Sum,
    output Cout,
    input [3:0] A,B,
    input Cin
wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin),


i used -s option with half_adder and as well as with ripple_adder_4bit but in both cases it didn't worked out.Still figuring out their use.

For reference i had used this link

| improve this answer | |

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.