After studying further i found that -c option can be used even for two files i.e. testbench.v and verilog.v.
we just need to create a ".txt" file with the name of the both the files written line after line like this
and pass it to iverilog.Further i wasn't able to get any test case with the usability of -s flag, though i tried to use it in followoing case but it gives no result and give wrong .vvp file which after executing produce no .vcd file.
output [3:0] Sum,
input [3:0] A,B,
i used -s option with half_adder and as well as with ripple_adder_4bit but in both cases it didn't worked out.Still figuring out their use.
For reference i had used this link